MT8940 ISO-CMOS
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 13)
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
CV/CVb (1.544 MHz) Setup time
CV/CVb (1.544 MHz) Hold time
t
25
ns
ns
S15
t
110
H15
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
V
OH
Boundary between ST-BUS channel 2 bit 4 and
channel 2 bit 3
F0b
C2o
V
OL
20 CYCLES
V
OH
V
OL
t
H15
t
S15
V
OH
CV
V
OL
t
H15
t
S15
V
OH
CVb
V
OL
Figure 13 - F0b from DPLL #2 is Looped Back as Input to DPLL #1 (T1 Line synchronized to ST-BUS)
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 14)
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
Master clocks input rise time
Master clocks input fall time
t
10
10
ns
ns
r
t
f
C
L
O
C
K
S
For DPLL #1, while operating to
provide the T1 clock signal.
Master clock period
(12.355MHz)
t
t
80.930 80.938 80.946
61.018 61.020 61.022
ns
ns
P12
P16
For DPLL #2, while operating to
provide the CEPT and ST-BUS
timing signals.
4
Master clock period
(16.388MHz)
5
6
Duty Cycle of master clocks
Lock-in Range (For each PLL)
45
50
55
%
With the Master clocks as shown
above.
-1.5
+1.04
Hz
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
t
f
r
2.4 V
1.5 V
0.4 V
Master clock
inputs
t
or t
P16
P12
Figure 14 - Master Clock Inputs
3-40
MITEL [ MITEL NETWORKS CORPORATION ]
