MH89790B
Preliminary Information
mode. This allows use of timeslot 16 for 64 kbit/s
Functional Description
common channel signalling.
Synchronization is
included within the CEPT bit stream in the form of a
bit pattern inserted into timeslot 0. The contents of
timeslot 0 alternate between the frame alignment
pattern and the non-frame alignment pattern as
described in Figure 3 below. Bit 1 of the frame
alignment and non-frame alignment bytes have
provisions for additional protection against false
synchronization or enhanced error monitoring. This
is described in more detail in the following section.
The MH89790B is
a
digital trunk interface
conforming to CCITT Recommendation G.704 for
PCM 30 and I.431 for ISDN. It includes features
such as insertion and detection of synchronization
patterns, optional cyclical redundancy check
(CRC-4) and far end error performance reporting,
HDB3 decoding and
associated or common
optional coding, channel
channel signalling,
programmable digital attenuation, and a two frame
received elastic buffer. The MH89790B can also
monitor several conditions on the CEPT digital trunk
which include the following: Loss of Signal (LOS)
indication, frame and multiframe synchronization,
received all 1’s alarms, data slips, as well as near
and far end framing and CRC errors.
In order to accomplish multiframe synchronization, a
16 frame multiframe is defined by sending four zeros
in the high order quartet of timeslot 16 frame 0, i.e.,
once every 16 frames (see Figure 4). The CEPT
format has four signalling bits, A, B, C and D.
Signalling bits for all 30 information channels are
transmitted in timeslot 16 of frames 1 to 15. These
timeslots are subdivided into two quartets (see Table
6).
The system interface to the MH89790B is a serial
bus that operates at 2048 kbit/s known as the
ST-BUS. This serial stream is divided into 125 µs
frames that are made up of 32 x 8 bit channels.
Cyclic Redundancy Check (CRC)
The line interface to the MH89790B consists of split
phase unipolar inputs and outputs which are
An optional cyclic redundancy check (CRC) has
been incorporated within CEPT bit stream to provide
additional protection against simulation of the frame
alignment signal, and/or where there is a need for an
enhanced error monitoring capability. The CRC
process treats the binary string of ones and zeros
contained in a submultiframe (with CRC bits set to
binary zero) as a single long binary number. This
supplied from/to
respectively.
a
bipolar line receiver/driver,
CEPT Interface
The CEPT frame format consists of 32, 8 bit
timeslots. Of the 32 timeslots in a frame, 30 are
defined as information channels, timeslots 1-15 and
17-31 which correspond to telephone channels 1-30.
An additional data channel may be obtained by
placing the device in common channel signalling
4
string of data is first multiplied by x then divided by
4
the polynomial x +x+1. This process takes place at
both the transmitter and receiver end of the link. The
remainder calculated at the receiver is compared to
the one received with the data over the link. If they
Bit Number
1
2
0
3
0
4
1
5
1
6
0
7
1
8
1
Timeslot 0 containing the
frame alignment signal
Reserved for
International
(1)
use
Timeslot 0 containing the
non-frame alignment signal
Reserved for
International
use
1
Alarm indication to the
remote PCM multiplex
equipment
See
Note
#3
See
Note
#3
See
Note
#3
See
Note
#3
See
Note
#3
(2)
Figure 3 - Allocation of Bits in Timeslot 0 of the CEPT Link
Note 1 : With CRC active, this bit is ignored.
Note 2 : With SiMUX active, this bit transmits SMF CRC results in frames 13 and 15.
Note 3 : Reserved for National use.
.
Timeslot 16 of frame 0
Timeslot 16 of frame 1
Timeslot 16 of frame 15
ABCD bits for
telephone
channel 1
ABCD bits for
telephone
channel 16
ABCD bits for
telephone
channel 15
(timeslot 15)
ABCD bits for
telephone
channel 30
(timeslot 31)
• • •
0000
XYXX
(timeslot 1)
(timeslot 17)
Figure 4 - Allocation of Bits in Timeslot 16 of the CEPT Link
4-190
MITEL [ MITEL NETWORKS CORPORATION ]
