GP2021
GPS 12 channel Correlator
Advance Information
DS4077 - 2.6 July 1996
The GP2021 is a 12 channel C/A code baseband
correlator for use in NAVSTAR GPS and GLONASS satellite
navigation receivers. The GP2021 complements the GP2015
and GP2010 C/A code RF downconverters available from
Mitel Semiconductor.
The GP2021 is compatible with most 16 bit and 32 bit
microprocessors, especially those from Motorola and Intel,
with additional on–chip support for the ARM60 32 bit RISC
processor. When the ARM60 is used, the on–chip memory
management functions allow implementation of a full GPS
receiver with minimal external logic.
The GP2021 allows individual channel de–activation, for
systems not requiring full 12 channel operation, to save power
and processor loading. Receiver power may be further
conserved by reducing the supply voltage to 2.2V under
battery backup. Although all system functions are disabled,
the 32.768kHz oscillator and Real Time Clock are maintained
for the microprocessor to estimate satellite visibility at power
on to reduce signal acquisition time.
A development system called the GPS Architect is
available as a basis for receiver design using the GP2021 and
associated products.
GP2021
PIN 1 IDENT
PIN 1
GQ80
Fig.1 Pin connections - top view
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DESCRIPTION
MULTI_FN_IO
POWER _GOOD
NRESET_OP
NARMSYS
XIN
XOUT
TXA
TXB
RXA
RXB
NROM / NC
NEEPROM / NC
NSPARE_CS / NC
V
DD
V
SS
NRAM / BC
NW0 / NC
NW1 / NC
NW2 / NC
NW3 / NC
NRD / NC
ARM_ALE / NC
DBE / NC
ACCUM_INT
MEAS_INT
NBW / WRPROG
NMREQ / DISCIP2
NOPC / NINTELMOT
NRW / DISCIP3
MCLK / NC
ABORT / MICRO_CLK
DISCIO
A22 / READ
VDD
VSS
A21 / NCS
A20 / WREN
A9
A8
A7
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DESCRIPTION
A6
A5
A4
A3
A2
A1 / ALE_IP
A0 / NRESET_IP
D0
D1
D2
D3
D4
D5
D6
V
DD
V
SS
D7
D8
D9
D10
D11
D12
D13
D14
D15
PLL_LOCK
VDD
DISCOP
V
SS
CLK_T
CLK_I
V
SS
SAMPCLK
V
DD
NBRAM / DISCIP4
SIGN0
MAG1
SIGN1
MAG1
DISCIP1
FEATURES
s
12 Fully Independent Correlation Channels
s
1PPS UTC Aligned Timing Output
s
On–Chip Dual UART and Real Time Clock
s
Compatible with most 16 and 32 bit Microprocessors
s
Memory Control Logic for ARM60 Microprocessor
s
Low Voltage, Low Current Power–Down Mode
s
Power Dissipation 150mW Typical
s
Compatible with GP2015 and GP2010 RF Front Ends
s
Battery Backup Voltage 2.2V (min)
APPLICATIONS
s
GPS Navigation Systems
s
High Integrity Combined GPS–GLONASS Receivers
s
GPS Geodetic Receivers
s
Time Transfer Receivers
ORDERING INFORMATION
GP2021/IG/GQ1R
RELATED PRODUCTS
PART
GP2015
GP2010
DW9255
P60ARM
GPS Architect
DESCRIPTION
GPS Receiver RF Front End
– TQFP 48 package
GlPS Receiver RF Front End
– PQFP 44 package
35.42MHz SAW Filter
32 bit RISC Microprocessor
GPS 12 Channel
Receiver Development System
DATASHEET
REFERENCE
DS4374
DS4056
DS3861
DS3553
DS4004
MITEL [ MITEL NETWORKS CORPORATION ]
