GP2021
Difference between Real and Complex_Input
Mode
The input mode is selected by theFRONT_END_MODE bit
Description
Recommended Master clock frequency
GP2021 internal clocking
1
MICRO_CLK 2 output frequency
mark : space
Pin No 76
Pin No 77
Pin No 78
Pin No 79
Input Signal Sampling Rate
SAMPCLK output frequency
mark : space
)
Notes.
1
2
The GP2021 interrupt and TIC timebase dividers are clocked by this resulting clock.
The MCLK output is derived from this signal. In ARM mode the phases of MCLK are stretched by the
Microprocessor Interface block.
in the SYSTEM_SETUP register. It defaults to Real_Input
mode at power up. The differences between Real and
Complex input mode are summarised in the following table.
Real_Input mode
40MHz
±
7
20MHz
1:1
SIGN 0
MAG 0
SIGN 1
MAG 1
5.714MHz
5.714MHz
4:3
Complex_Input mode
35MHz
÷
6
17.5MHz
1:1
SIGN_I
MAG_I
SIGN_Q
MAG_Q
5.833MHz
Not available
(held Low)
FUNCTIONAL DESCRIPTION
The GP2021 incorporates a 12 Channel GPS Correlator,
together with microprocessor support functions including a
Dual UART, a Real Time Clock and Memory Control Logic for
the ARM60 microprocessor. It can be configured for either
ARM System mode or Standard Interface mode. A block
diagram of the GP2021 is shown in Fig. 3.
Whilst in ARM System mode the Memory Control Logic
allows an ARM60 microprocessor to interface with the
Correlator, Real Time Clock, Dual UART and a variety of
memory devices (i.e.
ACCUM_INT
SRAM, EPROM, Flash and EEPROM), without the need for
external glue logic.
In Standard Interface mode the GP2021 allows most 16
and 32 bit microprocessors to interface with the Correlator,
Real Time Clock and Dual UART. More specifically, this mode
allows the interface to be configured for either Intel or Motorola
style microprocessor interfaces.
In the functional description which follows the correlator is
described first, followed by the peripheral functions.
MEAS_INT
RXA, RXB
TXA, TXB
D<15:0>
SIGN, MAG
SAMPCLK
CLK_T, CLK_I
12 CHANNEL
GPS
CORRELATOR
DUAL UART
REAL – TIME
CLOCK
CONTROL BUS
DATA BUS
MICRO_CLK
MICROPROCESSOR INTERFACE
POWER &
RESET
CONTROL
ARM SYSTEM
STANDARD
INTERFACE
NARMSYS
A<9:0>
NINTELMOT
WRPROG
POWER_GOOD
PLL_LOCK
WREN
MEMORY
INTERFACE
NRESET_OP
NRESET_IP
Fig. 3 : GP2021 block diagram
ARM60
INTERFACE
A<22:20>
ALE_IP
READ
NCS
XOUT
XIN
7
MITEL [ MITEL NETWORKS CORPORATION ]
