ACE9030
8·064 MHz Oscillator
RATIO, FROM BUS
: 100/337/825
CRYSTAL
FREQUENCY
(XO)
50 µA
50 µA
φ
UP
PHASE
DETECTOR
C8B
φ
DOWN
: 63/183/448
VCO
EXTERNAL
LOOP
FILTER
CHARGE
PUMPS
RATIO, FROM BUS
RANGE &
OFFSET
FROM BUS
8.064 MHz OUTPUT FREQUENCY
CLK8
Fig. 16 OSC8 Block Diagram
required it can be switched off by a Set-up command:
An 8·064 MHz oscillator OSC8 is provided to drive the
ACE9050 System Controller through pin CLK8. ACE9050
further drives the ACE9040 Audio Processor and the CL bus
clock via a ÷ 8 divider. OSC8 is locked to the crystal oscillator
by a phase locked loop with an external filter on pin C8B.
This loop can be programmed by a Set-up command to
givethecorrectoutputfrequencywithanyofthenormallyused
crystals. NotethatthesameSet-upcommandusesDATA1bit
D5 for the lock logic and bits D7 and D6 for the Discriminator
programming:
DATA1
DATA2
DATA3
xxxxxxxx
10xxxxx D0
xxxxxx00
where DATA2 bit D0 at LOW gives OSC8 OFF or DATA2 bit
D0 at HIGH gives OSC8 ON.
To allow for design and manufacturing tolerances the
VCO can be trimmed by two set-up commands, each of which
loads a 6 bit value in DATA1 into a control register. One sets
frequency “Range” (effectively the VCO gain but also with an
effect on the centre frequency):
DATA1
DATA2
DATA3
xxxxx D2 D1 D0
10xxxxxx
xx1xxx00
DATA1
DATA2
DATA3
where D2 D1 D0 act as in table 2. At power-on reset the setting
is D2 D1 D0 = 110, the values for a 15·36 MHz crystal, so that
the microcontroller is never clocked too fast with any of the
crystals and can then send the Set-up message to set D2 D1
D0 to the correct levels.
With a 14·85 MHz crystal it is not possible to both use a
high comparison frequency and get the exact 8·064 MHz
output, so two options are provided. The lower comparison
frequency will give the output exactly correct but will need
larger capacitors in the loop filter and the higher option allows
smaller capacitors and can improve close-in phase noise by
having a larger loop bandwidth, but gives a very small fre-
quency error - this error should have no effect in a practical
cellular terminal.
xx D5 D4 D3 D2 D1 D0
10x1xxxx
xxxxxx00
The other sets frequency “Offset” (effectively the VCO
centre frequency but also with an effect on the gain):
DATA1
xx D5 D4 D3 D2 D1 D0
DATA2
10xx1xxx
DATA3
xxxxxx00
The default values loaded by the power-on reset are
Offset = 0AHEX and Range = 21HEX and were chosen to help
ensure that the output clock on CLK8 does not run faster than
8·064MHzwhilebettervaluesaretobeloaded. Thesedefault
values can usually be left unchanged for normal operation.
The output of the phase comparator charge pump is on
pin C8B so that an external loop filter can be connected. This
loop filter then drives the VCO control voltage, also through
A Sleep command will not change the status of OSC8; if
enabled it will remain active when put into Sleep mode and
when returning to Normal mode. If the OSC8 oscillator is not
Command
Data D2 D1 D0
1 0 0
Crystal
Crystal
divider
÷100
÷825
÷337
PLL comp.
freq. (kHz)
128
OSC8
divider
÷63
÷448
÷183
÷63
Exact CLK8
output (MHz)
8·064
8·064
8·0639466
8·064
Error
(ppm)
0
0
–7
0
frequency
12·8 MHz
14·85 MHz
14·85 MHz
15·36 MHz
0 1 1
1 0 1
1 1 0*
18
44·065281
128
÷120
* Power up default
Table 2
19
MITEL [ MITEL NETWORKS CORPORATION ]
