ACE9030
The ADC data in the five registers is read in response to
a Normal command, with the two results to be output being
selected by two bits of DATA3:
The level for each DAC is set by a Normal command:
DATA1
DATA2
DATA3
DDDDDDDD
01xxxx D1 x
xxxx D3 D2 xx
DATA1
xxxxxxxx
DATA2
01xxxxxx
DATA3
xxxxxxY1Y0
where the data in DATA1 is loaded into DAC1 if DATA3 bit D3
is HIGH, into DAC2 if DATA3 bit D2 is HIGH, or into DAC3 if
DATA2 bit D1 is HIGH.
DAC1andDAC2remainactiveduringSleepmodebutthe
outputs are driven with reduced current capability; this will
slightly reduce the accuracy and will significantly increase the
settling time to any level change. DAC3 is powered down in
Sleep mode.
where Y1 Y0 are decoded to select:
Y1
0
0
1
1
Y0
0
1
0
1
Data requested
ADC5 & ADC1
ADC5 & ADC2A/B
ADC5 & ADC3A/B
ADC5 & ADC4
To power down DAC3 outside of Sleep mode, a Normal
command may be used:
DATA1
xxxxxxxx
DATA2
01xx D3 xxx
DATA3
xxxxxxxx
The requested data is then clocked out after a fixed delay,
with a preamble followed by the two results:
where DAC3 is active if DATA2 bit D3 is HIGH or powered
down if DATA2 bit D3 is LOW.
PREAMBLE
1010 Y1 Y0 0 L
RESULT 1
RRRRRRRR
RESULT 2
RRRRRRRR
L.F. Amplifiers
The Y1 Y0 code is output to confirm the data selection and
is the same as in the Normal command that requested the
data, detailed above, L is the Lock Detect status from the Lock
Detect Filter, and the two results are in the order ADC5 in
RESULT 1 and ADC1, 2, 3, or 4 in RESULT 2.
The level in the ADC1 register is continuously compared
with a threshold number such that if ADC1 is above this
threshold the output pin RXCD is driven HIGH and can be
used to indicate the presence of a received carrier. The
threshold is set by a Normal command on the bus, with the
value in DATA1:
Two identical low frequency amplifiers are provided; one
has inputs AMPP1 and AMPN1 driving output AMPO1, the
other has inputs AMPP2 and AMPN2 driving output AMPO2.
A typical use for AMP1 is as a linear amplifier to buffer the
DAC3 output to drive the transmit power control in a software
controlled loop with a power sensor input to ADC5.
AMP2 is typically used as a comparator to detect transmit
power independent of the software as a system integrity
check. The System Controller can then gate the presence of
transmitter power on AMPO2 with the absence of received
carrier on RXCD to detect a non-valid status and re-initialise
the system.
DATA1
DATA2
DATA3
DDDDDDDD
01xxxxxx
xxx1xxxx
Crystal Oscillator
A crystal oscillator maintaining circuit is provided on pins
CIN1 and CIN2 for use with a crystal at 12·8, 14·85 or
15·36 MHz depending on the cellular system chosen. The
circuit is designed for a crystal cut for a 20 pF load and with an
ESR less than 25 Ω. To ensure reliable fast start times for this
oscillator the bias current is increased significantly for the first
2047 cycles of oscillation after power-up, a restart command
or after an oscillator ON command and then automatically
changes to the lower normal level. The normal level has been
chosen to still guarantee start-up if the circuit should be
stopped by some external interference but to consume less
power than the fast start mode.
The buffered internal output of this oscillator is used in
severalsectionsofthechipandisreferredtoasXOinthisdata
sheet. This oscillator can be trimmed by using DAC1 and
DAC2 to control varicap diodes and so to pull the frequency,
the two DAC’s may be used to give separate AFC and
temperature compensation. A typical external circuit is shown
infigure14. EachDACprovidestypically30ppmtuningrange.
If preferred, an external oscillator can be used by driving
into CIN1 with CIN2 left open circuit. To allow this external
drive the internal oscillator should be shut down by using a
Set-up command with DATA3 bit D7 at LOW. The internal
oscillator is switched on at power-up, at restart, and by a Set-
up command with DATA3 bit D7 at HIGH:
IREF Bias Circuit
TosettheoperatingcurrentforseveralblocksintheRadio
Interface there is a bias pin IREF which should be connected to
the ground plane (VSS pins) via a resistor whose value de-
pendsonthesupplyvoltage, 68or100kΩ for3·75 Vor4·85 V
nominal VDD. The current into this pin is then mirrored to the
various functional blocks. To reduce the noise on this bias a
capacitor can be added from the IREF pin preferably to the
supply or alternatively to a good ground. A value of 82 nF
offers a good compromise between noise rejection and
power-up time.
D to A Converters
There are three 8-bit DAC’s with buffered outputs in the
ACE9030.
DAC1 and DAC2 have a high zero offset, a nominally
15 kΩ output series resistor, and are stable when driving up to
a 100 nF load capacitance.
DAC3 has a low zero offset and no output resistor. In
order to guarantee stability the capacitance of the load on
DAC3 must be no more than 30 pF.
The output resistors on DAC1 and DAC2 are used to form
part of a low pass filter and these DAC’s are intended to be
used to adjust the crystal frequency as given below under
Crystal Oscillator.
DATA1
DATA2
DATA3
xxxxxxxx
10xxxxxx
D7 xxxxx00
17
MITEL [ MITEL NETWORKS CORPORATION ]
