ACE9030
+ 2 X
XO
REF.CLOCK
(XO)
COMP. FREQ.
(MAIN)
INDICATES
ACTIVE EDGE
IN THE PHASE
COMPARATOR
TIME WINDOW
(MAIN)
UNLOCK
ADEQUATE LOCK
LOCK
PROG. DIVIDER
(MAIN)
MAIN LOCK
AUX.LOCK,
DERIVED SIMILARLY
LOCK
Fig. 13 Typical Lock Detect Waveforms
Pulses can occur on the LOCK signal at a rate up to the
higher of the Main and Auxiliary comparison frequencies, and
typically either 12·5 kHz for ETACS (50 kHz if Fractional-N is
used) or 30 kHz for AMPS so some extra filtering is needed to
get a clean lock indicator.
LOCKisfilteredbyfirstsamplingat504kHz(thebusclock
CL divided by two) and then counting the number of HIGH
samples in a pre-determined period. There are two selections
available for this counting period, approximately 160 µs (2
periods of 12·5 kHz or 8 of 50 kHz) or approximately 167 µs (5
periods of 30 kHz) which are set by a second counter, also
runningat504kHzandwithafixedmodulusof80or84. LOCK
is stable for each comparison period so the counts for each
comparisonfrequencyarealwaysinblocksof40for12·5 kHz,
10 for 50 kHz or 16 for 30 kHz.
The value in the LOCK sample counter is compared with
a threshold previously set by another bus command, to
determine if the loops are locked, the result is then output as
the last bit in the pre-amble word in the response to a Normal
command, before the ADC levels are given, as described in
the section Polling A to D converter.
The filter period is selected by the following Set-up
commandwhereDATA1bitD5 setstheperiodtooneofthetwo
values to suit whichever cellular system is to be used:
DATA1
xx D5 xxxxx
DATA2
10xxxxxx
DATA3
xx1xxx00
DATA1:5 = 0sets160 µsforETACS(Windowcount=80)and
DATA1:5 = 1 sets 167 µs for AMPS (Window count = 84).
The threshold is set by a Normal command:
DATA1bitsD7 toD1 forma7bitbinarynumberintherange
DATA1
D7 D6 D5 D4 D3 D2 D1 x
DATA2
01x1xxxx
DATA3
xxxxxxxx
0to127,whichisthethresholdvaluetobeloaded.Thewindow
period of 80 or 84 clock cycles sets the maximum count value
that can be found; the effect of unlock is to reduce the actual
count by at least one comparison period’s worth of samples
40, 10, or 16 so a suitable threshold can easily be chosen.
Assuming that the maximum sensitivity is required the thresh-
old should be set at just above the maximum count (80 or 84)
minus the effect of one unlock count (40, 10, or 16), to give
suggested thresholds of at least 42 (for 12·5 kHz) or 72 (for 50
kHz) or 70 (for 30 kHz). In each case any convenient number
between these suggestions and the maximum count may be
used as the selection is not critical.
Polling A To D Converter
A five channel polling Analog to Digital Converter is used
to monitor various analog levels, such as Received Signal
Strength, Transmitter Power, Temperature and Battery Volt-
age. The 8 bit ADC has a nominal range of 0·15 V to 3·45 V for
codes 00 to FF and is connected to each input channel, ADC1
to ADC5, in turn by the scanning logic. The results are put into
individual registers for reading by the microcontroller. The
successive approximation technique is used, with the bus
clock CL controlling both the timing of the conversion and also
the polling around the inputs. The voltage reference for the
ADC is shared with the three DAC’s and is derived from the
bandgap voltage through a trimming multiplier which can be
monitored on DOUT8 and is described in the section Band-
GapReference. Somechannelsarescannedmorefrequently
than others, with the pattern:
which repeats continuously. With clock CL at its normal
1008 kHz frequency, the scanning rates are 12·6 kHz for
ADC5, 6·3 kHz for ADC1 and 2·1 kHz for ADC2, 3 and 4.
Channels 2 and 3 each have two options, 2A, 2B and 3A,
3B as pins to connect to alternative points to monitor. The
selection is by a Set-up command:
DATA1
DATA2
DATA3
xxxxxxxx
10xxx D2 D1 x
xxxxxx00
where DATA2 bit D2 selects ADC3B when HIGH or ADC3A
when LOW for measurement by channel 3, and DATA2 bit D1
selects ADC2B when HIGH or ADC2A when LOW for meas-
urement by channel 2.
5, 1, 5, 2, 5, 1, 5, 3, 5, 1, 5, 4,
16
MITEL [ MITEL NETWORKS CORPORATION ]
