DATA SHEET
VSP 94x2A
2
Table 3–8: I C bus command description, continued
Bit
Subaddress 26h
D7-D0 IICINCR10-3
Name
Description
Belongs to 25h
[PP]
Subaddress 27h
D3
DISRES
[PP]
Reset of LL-PLL watchdog
‘0’: reset disabled
‘1’: reset enabled
D2-D0
IICINCR2-0
[PP]
Belongs to 25h
Subaddress 28h
D0
HRES
[PP]
Reset of LL-HPLL
‘0’: no reset
‘1’: reset
Note: reset automatically when written
Subaddress 29h
D7-D4
HSWIN
[PP]
Width of Noise Suppression Window of LL-HPLL
‘0000’: ±28 µs
‘0001’: ±24 µs
‘0010’: ±20 µs
‘0011’: ±16 µs
‘0100’: ±12 µs
‘0101’: ±8 µs
‘0110’: ±4 µs
‘0111’: dynamic windowing.
‘1000’: ±30 µs
‘1001’: ±27 µs
‘1010’: ±26 µs
‘1011’: ±22 µs
‘1100’: ±18 µs
‘1101’: ±14 µs
‘1110’: ±10 µs
‘1111’: ±6 µs
D3
D2
D1
D0
KD2
[PP]
Phase Detector Steepness
‘0’: steepness for normal TV operation mode
‘1’: steepness for operations where PPLIP is less than 288
d
HINCREXT
[PP]
HDTO testmode
‘0’: normal mode
‘1’: line-locked-clocks derived from frontend line-length
LMOD
[PP]
Selects line locked mode
‘0’: line locked-clocks derived from HPLL
‘1’: line-locked-clocks derived from frontend line-length
FMOD
[PP]
Selects freerun mode
‘0’: freerun-clocks derived from crystal
‘1’: freerun-clocks derived from HDTO
Adjustable frequency is only possible when set to ‘1’. When set to ‘0’, Backend
clock is always 36 MHz (9432/42: 18 MHz)
Micronas
Aug. 16, 2004; 6251-552-1DS
61
MICRONAS [ MICRONAS ]
