DATA SHEET
VSP 94x2A
2
Table 3–8: I C bus command description, continued
Bit
Name
Description
Subaddress 2Eh
D7-D6
CLKT
[PP]
Switch clkf20 and clkf40 to pads cvbs1 or bin2 (test only)
‘00’: no clock
‘01’: cvbs1 is output of clkf40
‘10’: bin2 is output of clkf20
‘11’: cvbs1 is output of clkf40 and bin2 is output of clkf20
D5
HWID
[PP]
Minimum width of H-sync
‘0’: 60*T
‘1’: 15*T
clkllf36
clkllf36
D4
HDTOTEST
[PP]
Test-bit for HPLL
‘0’: normal mode
‘1’: test mode
D3-D0
FILE
[PP]
Increment Freeze duration
‘0’: no freeze
‘15’: increment is frozen for 15 lines
Subaddress 2F
D1
LPFIPMD
[BP-DP]
Lines per field method
0: backend
1: frontend
D0
VINMTHD
[BP-DP]
Vertical ODC line counting
0: field delay
1: frame delay
Subaddress 30h
D7-D6
YCOR
[BP-DP]
Luminance Coring
‘00’: off
‘01’: 2
‘10’: 4
‘11’: 8
D5
CLKOUTON
[BP-DP]
Clkout Pad:
‘0’: off (tristate)
‘1’: on
D4-D2
THRESHC
[BP-DP]
Slope of DCTI function
‘000’: 255 (DCTI off)
‘001’: 2
‘010’: 3
‘011’: 4
‘100’: 6
‘101’: 8
‘110’: 10
‘111’: 12
D1-D0
ASCENTCTI
[BP-DP]
Gain of DCTI function
‘00’: 1/4
‘01’: 1/2
‘10’: 1
‘11’: 2
Micronas
Aug. 16, 2004; 6251-552-1DS
63
MICRONAS [ MICRONAS ]
