VSP 94x2A
DATA SHEET
2
Table 3–8: I C bus command description, continued
Bit
Name
Description
Subaddress 2Ah
D7-D6
D5-D4
D3-D0
KOIWID
[PP]
Window-Width of coincidence detector
‘00’: ±32 pixel (= ±0.9 µs for TV application)
‘01’: ±64 pixel (= ±1.8 µs for TV application)
‘10’: ±128 pixel (= ±3.6 µµs for TV application)
‘11’: ±256 pixel (= ±7.2 µs for TV application)
KOIH
[PP]
Hysteresis of coincidence detector
‘00’: 0 lines
‘01’: 8 lines
‘10’: 16 lines
‘11’: 32 lines
HTESTW
[PP]
Test bits for HPLL
00: default
Subaddress 2Bh
D7-D0 PPLIP9-2
Pixel per Line Input (Input-Processing)
[PP]
Granularity=4 pixel
‘175 ’: 700 (minimum)
d
‘576 ’: 2304
d
‘963 ’: 3852 (maximum)
d
Subaddress 2Ch
D7
SETSTABLL
[PP]
Stability Signal of LL_HPLL
‘0’: STABLL is generated by the HPLL
‘1’: STABLL is forced to 1
D6
FRFIX
[PP]
Freerunning clocks
‘0’: from fixed clock divider
‘1’: from freerunning DTO (adjustable clocks)
D4
LIMEN
[PP]
Limiter enable
‘0’: A32 behavior for LIMIP and LIMII
‘1’: normal LIMII and LIMIP characteristic
D3
FKOI
[PP]
Force Coincidence Bit
‘0’: coincidence bit dynamically changed
‘1’: coincidence bit forced to 1
D2
FKOIHYS
[PP]
Force coincidence hysteresis bit
‘0’: coincidence hysteresis bit dynamically changed
‘1’: coincidence hysteresis bit forced to 1
D1-D0
PPLIP1-0
[PP]
Belongs to 2Bh
Subaddress 2Dh
D7-D4
FION
[PP]
Increment Freeze before V-sync
‘0’: no freeze
‘15’: freeze starts 15 lines before V-sync
D0
LNL
[PP]
Dynamic Time Constant Control
‘0’: linear mode
‘1’: non linear mode
62
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
