DATA SHEET
VSP 94x2A
The PLL settings for different operation modes can be
seen in Table 2–18.
Dependent on input signal (50 Hz or 60 Hz), the line-
locked clock is changing slightly (e.g. from 27 MHz to
27.18 MHz). To have no artifacts when switching
between locked and freerun operation, it is possible to
change the FRINC parameter, after the input TV stan-
dard has been detected safely. In case the IC is oper-
ating in horizontal locked OR freerunning mode only,
this adaptivity is not required.
Table 2–18: Recommended LL-PLL settings for normal TV-application
Operation
Input
50 Hz
60 Hz
50 Hz
60 Hz
PPLIP*4
PPLOP*4
IICINCR
FRINCR
349525
351953
262144
263892
349525
351953
262144
263892
CLKB36 [MHz]
f [kHz]
H
100/120 Hz
(analog out)
2304
1152
349525
36
31.250
31.468
31.250
31.468
15.625
15.734
15.625
15.734
36.25
27
100/120 Hz
(digital out)
1728
2304
1728
864
262144
349525
262144
27.18
18
50/60 Hz (ana- 50 Hz
log out)
1152
864
60 Hz
18.125
13.5
13.59
50/60 Hz (digi- 50 Hz
tal out)
60 Hz
Micronas
Aug. 16, 2004; 6251-552-1DS
33
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