VSP 94x2A
DATA SHEET
xin
sda scl
xout
S
o
u
r
c
e
cvbs1
cvbs2
cvbs3
cvbs4
36.0F MHz
72,0 MHz
PP
(PLL
27,0 MHz
ADC
AGC
processing
block)
vout
hout
36,0B MHz
cvbs5
S
e
l
e
c
t
cvbs6
ADC
40,5 MHz
20,25 MHz
cvbs7
cvbso1
cvbso2
cvbso3
OUT 27.0
ODC
I²C
CP
OSC
HPRESCALE
TNR
DAC
DAC
DAC
(CVBS
processing block)
O
u
t
7
2
ayout
auout
avout
M
C
-
M
C
-
CD
S
o
u
r
c
e
b/u1
g/y1
r/v1
FP
BP
(Front end processing block)
(Back end processing block)
1
2
HPOSTSCALE
RGB
fbl/hin1
DELAY
PICIMPROVE
ADC
ADC
ADC
b/u2
g/y2
r/v2
S
e
l
e
c
t
VSP 94x2A
fbl/hin2
ADC
vin
hout50
vout50
2
Fig. 3–1: I C Bus Clock Domains
2
Table 3–6: I C bus characterization
Subaddress
00h
Default
AAh
CAh
B0h
C8h
16h
10h
20h
01h
F0h
3Eh
00h
A0h
00h
90h
80h
00h
20h
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Take-over Subaddress
Default
44h
00h
FFh
1Fh
F4h
44h
00h
FFh
AAh
AAh
05h
00h
60h
60h
90h
00h
04h
R/W
Take-over
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
V40
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
01h
V40
02h
V40
03h
V40
04h
V40
05h
V40
06h
V40
07h
V40
08h
NTO
09h
NTO
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
NTO/HS
NTO/rstyp
NTO
NTO
NTO
NTO/HS
NTO
10h
36
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
