DATA SHEET
VSP 94x2A
The selection between freerunning and locked clocks
may be forced or selected to be dependent on PLL
conditions. Please refer to Fig. 2–41
with this sampling clock. The clock output can be dis-
abled by CLKOUTON. Additionally a 20.25 MHz clock
can be output to pin 74 (656hin/clkf20) to supply other
ICs (e.g. PiP) with the same clock (CLKF2PAD). When
enabled, 656-input with separate H/V-sync is not pos-
sible. For 656-output operation, CLKB36 is given to pin
9 (656clk).
A
clock
output
of
27 MHz
(single-scan
version:13.5 MHz) is possible (pin 27:clkout). This
clock is 3/4 of CLKB36. HOUT and VOUT are in line
Table 2–17: Clock system
Name
Clock
Nominal Frequency
‘H-/V-
locked’
Mode
‘H-freerunning- ‘H-/V-
V-locked’
Mode
freerunning’
Mode
CLKF20
CLKF40
CVBS front-end
20.25 MHz
40.5 MHz
FR
FR
FR
FR
FR
RGB front-end,
input processing
FR
CLKB36
CLKB72
CLKB27
Output and dis-
play processing
9402: 36 MHz (analog out)
9412: 27 MHz (digital out)
LL
LL
LL
FR
FR
FR
FR
FR
FR
Oversampling,
DAC
9402: 72 MHz
9412: 54 MHz
CLKOUT-pin
9402: 27 MHz
9412: 20.25 MHz
Front-end
PLL
STAB=0 and
AUTOFREERUN=1x
CVBS
Freerun
Generator
freerunning
clocks
SETSTABLL
HOUTFR
0
1
0
1
CLKBxx
1
0
yes
no
locked
clocks
LL-PLL
STABLL
(indicates PLL stability)
Fig. 2–41: Conditions for Freerunning/Locked Switching
Micronas
Aug. 16, 2004; 6251-552-1DS
31
MICRONAS [ MICRONAS ]
