ADVANCE INFORMATION
VPC 323xD, VPC 324xD
2
I C Sub- Number
Mode
Function
Default
Name
address
of bits
h’23
16
w/r
OUTPUT STRENGTH:
OUTSTR
PADSTR
bit[3:0] 0..15
output pin strength
0
0
(0 = strong, 15 = weak)
bit[9:4]
32
address of output pin
FIFO control pins FFIE, FFOE, FFWR,
FFRE and FFRSTWR
PADADD
33
0/1
SYNC pins AVO, HS, HC, INTERLACE, VS
read/write output strength
reserved (set to 0)
bit[10]
bit[15:11]
0
0
PADWR
h’30
h’24
8
8
w/r
w/r
V-SYNC DELAY CONTROL:
bit[7:0] VS delay (8 LLC clock cycles per LSB)
VSDEL
VSDEL
0
656 Interface
656 OUTPUT INTERFACE
OUT656
bit [0]
bit [1]
bit [2]
1
disable hor. & vert. blanking of invalid
data in 656 mode
use vertical window as VFLAG
use vsync as VFLAG
enable suppression of 656-headers
during invalid video lines
0 DBLNK
0
1
0 VSMODE
0 HSUP
bit [3]
bit [4]
bit [5]
enable ITU-656 output format
LLC1/LLC2 used as reference clock
output mode: DIGIT 3000 / LLC
0 656enable
0 DBLCLK
1 OMODE
0/1
0/1
Sync Generator
h’21
16
w/r
LINE LENGTH:
bit[10:0]
LINE LENGTH register
1295 LINLEN
In LLC mode, this register defines the
cycle of the sync counter which generates
the SYNC pulses.
In LLC mode, the synccounter counts from
0 to LINE LENGTH, so this register has to
be set to “number of pixels per line –1”.
In DIGIT3000 mode, LINE LENGTH has to
be set to 1295 for correct adjustment of
vertical signals.
bit[15:11]
reserved (set to 0)
h’26
h’27
16
16
w/r
w/r
HC START:
bit[10:0]
HC START defines the beginning of the
HC signal in respect to the value of the
sync counter.
50 HCSTRT
800 HCSTOP
bit[15:11]
bit[10:0]
reserved (set to 0)
HC STOP defines the end of the HC signal
in respect to the value of the sync counter.
reserved (set to 0)
bit[15:11]
Micronas
33
MICRONAS [ MICRONAS ]
