VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 3–1: Control and status registers
2
I C Sub- Number
Mode
Function
Default
Name
address
of bits
FP Interface
h’35
8
r
FP status
bit [0]
bit [1]
–
FPSTA
write request
read request
busy
bit [2]
h’36
h’37
h’38
16
16
16
w
bit[8:0]
bit[11:9]
9-bit FP read address
reserved, set to zero
–
–
–
FPRD
FPWR
FPDAT
w
bit[8:0]
bit[11:9]
9-bit FP write address
reserved, set to zero
w/r
bit[11:0]
FP data register, reading/writing to this
register will autoincrement the FP read/
write address. Only 16 bit of data are
transferred per I2C telegram.
Black Line Detector
h’12
16
w/r
read only register, do not write to this register! After reading,
LOWLIN and UPLIN are reset to 127 to start a new measure-
ment.
–
BLKLIN
bit[6:0]
bit[7]
number of lower black lines
always 0
LOWLIN
bit[14:8]
bit[15]
number of upper black lines
normal/black picture
UPLIN
BLKPIC
0/1
Pin Circuits
h’1F
16
w/r
SYNC PIN CONTROL:
bit[2:0] 0..7 reserved (set to 0)
TRPAD
0
0
0
0
0
0
0
0
bit[3]
bit[4]
bit[5]
0/1
0/1
0
pushpull/tristate for AVO Pin
pushpull/tristate for other video SYNC Pins
reserved (set to zero)
AVODIS
SNCDIS
CLOCK/FIFO PIN CONTROL:
bit[6]
bit[7]
bit[8]
bit[9]
0/1
0/1
0
pushpull/tristate for LLC1
pushpull/tristate for LLC2
reserved (set ot 0)
LLC1DIS
LLC2DIS
0/1
pushpull/tristate for FIFO control pins
FFSNCDIS
LUMA/CHROMA DATA PIN (LB[7:0], CB[7:0]) CONTROL:
0
0
0
0
bit[10]
0/1
0/1
tristate/pushpull for Chroma Data pins
tristate/pushpull for Luma Data pins
reserved (set to 0)
CDIS
YDIS
bit[11]
bit[15:12]
h’20
8
w/r
SYNC GENERATOR CONTROL:
SYNCMODE
bit[1:0] 00
AVO and active Y/C data at same time
0
AVOPRE
01
10
11
0/1
0/1
0/1
0/1
0/1
0/1
AVO precedes Y/C data one clock cycle
AVO precedes Y/C data two clock cycles
AVO precedes Y/C data three clock cycles
positive/negative polarity for HS signal
positive/negative polarity for HC signal
positive/negative polarity for AVO signal
positive/negative polarity for VS signal
positive/negative polarity for HELP signal
positive/negative polarity for INTLC signal
bit[2]
bit[3]
bit[4]
bit[5]
bit[6]
bit[7]
0
0
0
0
0
0
HSINV
HCINV
AVOINV
VSINV
HELPINV
INTLCINV
32
Micronas
MICRONAS [ MICRONAS ]
