ADVANCE INFORMATION
VPC 323xD, VPC 324xD
Table 2–12: Settings for Free-Running Mode
Control bit
Function
VPCsingle
VPCpip
VPCmain
predef.
write
PIP
write main
pic.
all other
mode 6, 10 modes
bit[11] of LLC_CLKC
(FP h’6a)
enable/disable
LLC PLL
1
0
0
0
1
1
0
0
bit[15] of AVO START
(I2C h’28)
enable/disable free-
running sync mode
1
0
2.12.9. External Field Memory
The requirements of the external field memory are:
As serial write and serial read clock (SWCK and
SRCK, respectively) of the field memory the line
locked clocks LLC1 and/or LLC2 are used.
– FIFO type access with reset
– write mask function: The increasing of the write
address pointer and the over writing of the data
should be controlled separately.
– output disable function: tri-statetable outputs
For PIP applications, VPC 32xxD supports 4:1:1 or
4:2:2 chrominance format. Table 2–13 shows the typi-
cal memory size for a 13.5 and 16 MHz system clock
application.
Table 2–13: Word length and minimum size of the field
memory
Chromi-
nance
Word
length
Memory size
format
[bit]
[word]
[bit]
4:1:1
4:2:2
12
16
245376
245376
2944512
3926016
The following 5 signals are generated by VPC 32xxD
to control the external field memory:
RSTWR (reset write/read) resets the internal write/
read address pointer to zero.
WE (write enable) is used to enable or disable incre-
menting of the internal write address pointer.
IE (input enable) is used to enable writing data from
the field memory input pins into the memory core, or to
disable writing and thereby preserving the previous
content of the memory (write mask function).
RE (read enable) is used to enable or disable incre-
menting the internal read address pointer.
OE (output enable) is used to enable or disable data
output to the output pins.
Micronas
29
MICRONAS [ MICRONAS ]
