PRELIMINARY DATA SHEET
VDP 31xxB
H
flyback
PLL3
1:64
&
main
skew
measure–
ment
phase
comparator
&
DAC
&
LPF
sinewave
generator
H
drive
sync
MSY
DCO
output
generator
stage
lowpass
blanking, clamping, etc.
Standby clock
display
timing
PLL2
composite
sync
CSY
phase
front
sync
interface
generator
line
counter
comparator
DCO
FSY
&
lowpass
V
vertical reset
clock & control
flyback
PWM
15 bit
E/W
ouput
E/W
correction
vertical
serial
data
VDATA
PWM
15 bit
sawtooth
V
output
Fig. 2–28: Deflection processing block diagram
line
[0]
line
Parity
Parity
M1
M2
[7]
line
[8]
not not not not not
used used used used used
V
F
input
analog
video
V: Vert. blanking
0 = off
(not in scale)
1 = on
Field #
F:
M1 M2
MSY
timing reference for PICTURE bus
– chroma multiplex sync
– active picture data after xxx clocks
0 = Field 1
1 = Field 2
line: Field line #
1...N
Fig. 2–29: Main sync format
Micronas
27
MICRONAS [ MICRONAS ]
