VDP 31xxB
PRELIMINARY DATA SHEET
2.9.5. Fast Blank Monitor
2.9.6. Half Contrast Control
The presence of external analog RGB sources can be
detected by means of a fast blank monitor. The status of
the selected fast blank input can be monitored via an I C
busregister. Thereisa2bitinformation, givingstaticand
dynamic indication of a fast blank signal. The static bit is
directly reading the fast blank input line, whereas the dy-
namic bit is reading the status of a flip-flop triggered by
the negative edge of the fast blank signal.
Insertion of transparent text pages or OSD onto the vid-
eo picture is often difficult to read, especially if the video
contrast is high. The VDP 31xxB allows contrast reduc-
tion of the video background by means of a half contrast
input (HCS pin). This input can be supplied with a fast
switching signal (similar to the fast blank input), typically
defining a rectangular box in which the video picture is
displayedwithreducedcontrast. TheanalogRGBinputs
are still displayed with full contrast.
2
With this monitor logic it is possible to detect if there is
an external RGB source active and if it is a full screen in-
sertion or only a box. The monitor logic is connected di-
rectly to the FBLIN1 or FBLIN2 pin. Selection is done via
The HCS input is multiplexed with the PORT0 input/out-
put on the same pin, selection is done via I C-bus regis-
2
ter. If the HCS input is selected, then the port function of
this pin is disabled and writing data into PORT0 will have
2
I C bus register.
2
no effect. If the HCS input is not selected, the I C-bus
register bits HCSFOH and HCSPOL must be used to
disable the half contrast function.
FBFOH1 FBFOL1
FBPOL
FBPRIO
HCSPOL
FBLIN1
#
HCS
FB
int
HCS intern
#
Fast
Blank
Monitor
Fast
Blank
Selection
FBLIN2
HCSEN HCSFOH
#
Fig. 2–26: Half Contrast Switch Logic
FBFOH2 FBFOL2
FBMON
2.10. IO Port Expander
Fig. 2–25: Fast Blank Selection Logic
The VDP 31xxB provides a general purpose IO port to
control and monitor up to seven external signals. The
port direction is programmable for each bit individually.
2
Via I C bus register it is possible to write or read each
2
port pin. Because of the relatively low I C bus speed,
only slow or static signals can be handled.
The port signals are multiplexed with other signals to
minimize pin count. PORT0 is multiplexed with the HCS
input signal, PORT1 is multiplexed with the FSY output
signal, PORT[6:2] are multiplexed with the color bus in-
putCOLOR[4:0]. Thepinconfigurationisprogrammable
2
viaI Cbusregister. Allregisterbitscanbereadback, the
default configuration after reset is input on PORT[1:0]
and COLOR[4:0] enabled.
24
Micronas
MICRONAS [ MICRONAS ]
