VDP 31xxB
PRELIMINARY DATA SHEET
2.11. Synchronization and Deflection
stage the frequency is divided down to give drive-pulse
period and width. In standby mode, the output stage is
driven from an internal 1 MHz clock that is derived from
the 5 MHz clock signal and a fixed drive pulse width is
used. When the circuit is switched out of standby
operation, the drive pulse width is programmable. The
horizontal drive uses an open drain output transistor.
The synchronization and deflection processing is
distributed over front-end and back-end. The video
clamping, horizontal and vertical sync separation and all
video related timing information are processed in the
front-end. Most of the processing that runs at the hori-
zontal frequency is programmed on the internal Fast
Processor (FP). Also the values for vertical and East/
West deflection are calculated by the FP software.
The Main Sync (MSY) signal that is generated from
PLL3 is a multiplex of all display-related data
(Fig. 2–29). This signal is intended for use by other pro-
cessors, e.g. a PIP processor can use this signal to ad-
just to a certain display position.
The information extracted by the video sync processing
is multiplexed onto the hardware front sync signal (FSY)
and distributed internally to the rest of the video proces-
sing system.
2.11.2. Horizontal Phase Adjustment
The data for the vertical deflection, the sawtooth and the
East/West correction signal is calculated in the front
end. The data is transferred to the back-end by a single
wire interface.
This section describes a simple way to align PLL phases
and the horizontal frame position.
1. The parameter NEWLIN in the front-end has to be
adjusted. The minimum possible value is 34 (recom-
mended for a standard 4:3 signal).
The display related synchronization, i.e. generation of
horizontal and vertical drive and synchronization of hori-
zontal and vertical drive to the video timing extracted in
the front-end, are implemented in hardware in the back-
end.
2. With HDRV, the duration of the horizontal drive pulse
has to be adjusted.
3. With POFS2, the clamping pulse for the analog RGB
input has to be adjusted to the correct position, e.g.
the pedestal of the generator signal.
2.11.1. Deflection Processing
4. With POFS3, the horizontal position of the analog
RGB signal (from SCART) has to be adjusted.
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2–28). This block
contains two phase-locked loops:
5. WithHPOS, thedigitalRGBoutputsignal(fromVPC)
has to be adjusted to the correct horizontal position.
– PLL2 generates the horizontal and vertical timing, e.g.
blanking, clamping and composite sync. Phase and
frequency are synchronized by the front sync signal.
6. With HBST and HBSO, the start and stop values for
the horizontal blanking have to be adjusted.
Note: The processing delay of the internal digital video
path differs depending on the comb filter option of the
VDP 31xxB. The versions with comb filter have an addi-
tional delay of 35 clock cycles. Therefore, the timing of
theexternalanalogRGBsignalshastobeadjusted(with
POFS2 and POFS3) according to the actual hardware
version of the VDP 31xxB. The hardware version can be
read out via FP subaddress 0xF1.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal output
stage. Phase and frequency are synchronized by the
oscillator signal of PLL2.
The horizontal drive circuitry uses a digital sine wave
generator to produce the exact (subclock) timing for the
drive pulse. The generator runs at 1 MHz; in the output
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