PRELIMINARY DATA SHEET
VDP 31xxB
2
Table 3–1: I C control and status registers of front-end
2
I C Sub Number
address of bits
Mode
Function
Default Name
FP INTERFACE
h’35
8
r
FP status
bit [0]
bit [1]
FPSTA
write request
read request
busy
bit [2]
h’36
h’37
h’38
16
16
16
w
w
bit[8:0]
bit[11:9]
9-bit FP read address
reserved, set to zero
FPRD
FPWR
FPDAT
bit[8:0]
bit[11:9]
9-bit FP write address
reserved, set to zero
w/r
bit[11:0]
FP data register, reading/writing to this
register will autoincrement the FP read/
write address. Only 16 bit of data are
2
transferred per I C telegram.
BLACK LINE DETECTOR
h’12
16 w/r read only register, do not write to this register!
BLKLIN
after reading, LOWLIN and UPLIN are reset to 127 to start a new
measurement
LOWLIN
bit[6:0]
bit[7]
number of lower black lines
always 0
UPLIN
BLKPIC
bit[14:8]
bit[15]
number of upper black lines
normal/black picture
0/1
PIN CIRCUITS
h’1F
16
w/r
INTLC & PORT pins:
TRPAD
SNCSTR
bit[2:0]
0..7
output strength for INTLC & PORT Pins
(7 = tristate, 6 = weak ... 0 = strong)
reserved (set to 0)
pushpull/tristate for INTLC Pin
synchronization/no synchronization with
horizontal MSY for signal INTLC
reserved (set to 0)
0
bit[3]
bit[4]
bit[5]
0
0/1
0/1
0
0
SNCDIS
VASYSEL
bit[15:6]
h’20
h’24
8
w/r
SYNC GENERATOR CONTROL:
SYNMODE
INTLCINV
bit[6:0]
bit[7]
0
0/1
reserved (set to 0)
positive/negative polarity for INTLC signal
0
PRIORITY BUS
w/r
8
priority bus ID register and control
PRIOMODE
PID
PRIOSTR
bit [2:0]
bit [4:3]
bit [5]
0..7
0..3
0/1
0/1
priority ID, 0 highest
pad driver strength, 0 (strong) to 3 (weak)
reserved (set to 0)
0
0
0
0
bit [6]
source for prio request:
PIDSRC
PIDE
active video/clamp_to_1
disable/enable priority interface, if disabled
frontend is disconnected from priority bus!
bit [7]
0/1
0
Micronas
31
MICRONAS [ MICRONAS ]
