欢迎访问ic37.com |
会员登录 免费注册
发布采购

VCT3832A 参数 Datasheet PDF下载

VCT3832A图片预览
型号: VCT3832A
PDF下载: 下载PDF文件 查看货源
内容描述: 视频/控制/图文电视IC系列 [Video/Controller/Teletext IC Family]
分类和应用: 电视
文件页数/大小: 172 页 / 2219 K
品牌: MICRONAS [ MICRONAS ]
 浏览型号VCT3832A的Datasheet PDF文件第94页浏览型号VCT3832A的Datasheet PDF文件第95页浏览型号VCT3832A的Datasheet PDF文件第96页浏览型号VCT3832A的Datasheet PDF文件第97页浏览型号VCT3832A的Datasheet PDF文件第99页浏览型号VCT3832A的Datasheet PDF文件第100页浏览型号VCT3832A的Datasheet PDF文件第101页浏览型号VCT3832A的Datasheet PDF文件第102页  
VCT 38xxA  
ADVANCE INFORMATION  
If the mapping logic does not find any address match,  
the TPU address is directly put on the CPU address  
bus with A19 set to “1”. In case of multiple matches,  
the priority is map1 > map2 > map3 > map4.  
76: 1E0C  
79: 1E0D  
82: 1E0E  
85: 1E0F  
77: CMP1H  
80: CMP2H  
83: CMP3H  
86: CMP4H  
78: Compare 1 High Byte  
81: Compare 2 High Byte  
84: Compare 3 High Byte  
87: Compare 4 High Byte  
bit  
7
6
5
4
3
CA19  
1
2
CA18  
1
1
CA17  
1
0
CA16  
1
12  
w
CMP n  
match  
=
reset  
12  
12  
A[19:8]  
&
CA19 to 8 Compare Address  
Masked TPU address is compared with this value.  
MASK n  
&
&
88: 1E10  
91: 1E11  
94: 1E12  
97: 1E13  
89: MAP1L  
92: MAP2L  
95: MAP3L  
98: MAP4L  
90: Map 1 Low Byte  
93: Map 2 Low Byte  
96: Map 3 Low Byte  
99: Map 4 Low Byte  
1  
A[19:8]  
12  
MAP n  
bit  
w
7
6
5
4
3
2
1
MPA9  
1
0
MPA8  
1
MPA15 MPA14 MPA13 MPA12 MPA11 MPA10  
1
n: mapping logic 1 to 4  
reset  
1
1
1
1
1
Fig. 5–9: DMA mapping logic  
100: 1E14  
101: MAP1H  
104: MAP2H  
107: MAP3H  
110: MAP4H  
102: Map 1 High Byte  
105: Map 2 High Byte  
108: Map 3 High Byte  
111: Map 4 High Byte  
103: 1E15  
106: 1E16  
109: 1E17  
5.9.1. DMA Registers  
bit  
7
6
5
4
3
2
1
0
40: 1E00  
43: 1E01  
46: 1E02  
49: 1E03  
41: MASK1L  
44: MASK2L  
47: MASK3L  
50: MASK4L  
42: Mask 1 Low Byte  
45: Mask 2 Low Byte  
48: Mask 3 Low Byte  
51: Mask 4 Low Byte  
w
MPA19 MPA18 MPA17 MPA16  
1
reset  
1
1
1
MPA19 to 8 Map Address  
Matching TPU address is replaced with this value.  
bit  
7
MA15  
1
6
MA14  
1
5
MA13  
1
4
MA12  
1
3
MA11  
1
2
MA10  
1
1
MA9  
1
0
MA8  
1
w
reset  
112: 1E18  
113: DMAIM  
114: DMA Interface Mode  
bit  
7
DMAEN  
0
6
5
4
3
2
1
0
w
MAP4E MAP3E MAP2E MAP1E  
52: 1E04  
53: MASK1H  
56: MASK2H  
59: MASK3H  
62: MASK4H  
54: Mask 1 High Byte  
57: Mask 2 High Byte  
60: Mask 3 High Byte  
63: Mask 4 High Byte  
reset  
0
0
0
0
55: 1E05  
58: 1E06  
61: 1E07  
DMAEN  
w1:  
w0:  
DMA Enable  
Enable DMA Interface  
Disable DMA Interface  
bit  
7
6
5
4
3
MA19  
1
2
MA18  
1
1
MA17  
1
0
MA16  
1
w
reset  
MAPxE  
w1:  
w0:  
Mapping Logic x Enable  
Enable mapping logic x  
Disable mapping logic x  
MA19 to 8 Mask Address  
TPU address is masked with this value.  
64: 1E08  
67: 1E09  
70: 1E0A  
73: 1E0B  
65: CMP1L  
68: CMP2L  
71: CMP3L  
74: CMP4L  
66: Compare 1 Low Byte  
69: Compare 2 Low Byte  
72: Compare 3 Low Byte  
75: Compare 4 Low Byte  
bit  
7
CA15  
1
6
CA14  
1
5
CA13  
1
4
CA12  
1
3
CA11  
1
2
CA10  
1
1
CA9  
1
0
CA8  
1
w
reset  
98  
Micronas  
 复制成功!