ADVANCE INFORMATION
VCT 38xxA
A[18:0]
D[7:0]
RWQ
Address
Mapping
PH2
RWQ
TPU
SRAM
Interface
DMA Interface
RDY
BE
CPU
RWQ
DB[7:0]
ADB[19:0]
Fig. 5–7: Block diagram of DMA interface
In general, all TPU addresses are mapped into bank
16 to 31 of the CPU address space by forcing the MSB
of the address bus to “1” (see Fig. 5–8). Additionally
4 memory segments can be mapped into any address
area by programming a set of DMA registers (see
Fig. 5–9).
Special care should be taken when mapping TPU
addresses into the RAM area of bank 0. Any over-
lap between TPU memory (e.g. OSD Bank) and
controller memory (e.g. non zero page variables)
must be avoided.
TPU Address Bus
A[18:8]
A19 = “1”
map
4
match4
match3
match2
match1
map
3
map
2
map
1
12
12
12
12
12
3
Decoder
Mux 1:5
12
ADB[19:8]
Fig. 5–8: DMA address mapping
Micronas
97
MICRONAS [ MICRONAS ]
