VCT 38xxA
ADVANCE INFORMATION
5.7.4. External Reset Sources
If the source of one of these interrupts is still active,
resetting the interrupt flag will not work and no further
interrupt will be generated.
As long as the reset input comparator on the pin
RESQ detects the Low level, the VCT 38xxA is in reset
state. On this pin, external reset sources may be wire-
ored with the internal reset sources, leading to a sys-
tem-wide reset signal combining all system reset
sources.
I2CEN
r/w1:
I2C Enable
Enable I2C output from FE/BE.
Disable I2C output.
r/w0:
DCOCLP DCO clamping
r/w1:
r/w0:
DCO input clamped to 0.
DCO input controlled by front-end.
5.7.5. Summary of Module Reset States
After reset, the controller modules are set to the follow-
ing reset states:
SELCLK
r/w1:
Select clock source
From PLL.
r/w0:
From DCO.
Table 5–6: Status after reset
RESDIS
r/w1:
r/w0:
Reset Disable
Disable internal CPU reset.
Enable internal CPU reset.
Module
Status
CPU
CPU Fast mode.
RESOUT
w1:
w0:
RESQ Output
RESQ output active.
RESQ output inactive.
Interrupt
Controller
Interrupts are disabled. Priority reg-
isters, request flip-flops and stack
are cleared.
Ports
Normal mode. Output is tristate.
31: 1F00
32: CSW0
33: Clock, Supply & Watchdog Regis-
ter 0
Watchdog
Switched off. SW activation is pos-
sible.
bit
w
7
x
x
6
5
x
x
4
x
x
3
x
x
2
x
x
1
x
x
0
CSA
1
x
reset
x
Clock
monitor
EMU IC: Active. SW may toggle.
normal IC: Permanently active.
This register controls the Supply and Clock Supervi-
sion modules.
5.7.6. Reset Registers
CSA
w1:
w0:
Clock and Supply Supervision Active
Both Enabled.
Both Disabled.
28: 1F07
29: RC
30: Reset Control Register
bit
w
7
6
5
4
3
2
1
0
ALI
ALI
0
VSI
VSI
0
TPUI
TPUI
0
I2CEN DCOCLP SELCLK RESDIS RESOUT
r
I2CEN DCOCLP SELCLK RESDIS
0
34: 1F60
35: CSW1
36: Clock, Supply & Watchdog Regis-
ter 1
reset
0
1
0
0
0
bit
r
7
6
5
4
3
2
1
0
This register controls the reset logic and clock genera-
tion.
x
x
x
x
x
x
x
WDRES
w
Watchdog Time and Trigger Value
reset
1
1
1
1
1
1
1
1
ALI
r1:
r0:
Alarm Interrupt
Alarm was interrupt source
no pending alarm interrupt
reset alarm interrupt
This register controls the Watchdog module. Only val-
ues between 1 and 255 are allowed.
w1:
WDRES
r1:
w:
Watchdog Reset Source
Watchdog was reset source.
Any write access to CSW1 resets this
flag.
VSI
r1:
r0:
VSUPD Voltage Supervision Interrupt
VSUPD supervision was interrupt source
no pending VSUPD supervision interrupt
reset VSUPD supervision interrupt
w1:
First write the desired watchdog time value to this reg-
ister. On further writes, to retrigger the Watchdog,
alternatingly write a value (not necessarily the former
time value) and its bit complemented value. Never
change the latter value.
TPUI
r1:
r0:
TPU Watchdog Interrupt
TPU watchdog was interrupt source
no pending TPU watchdog interrupt
reset TPU interrupt flag
w1:
94
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