ADVANCE INFORMATION
VCT 38xxA
Within the evaluation period (see Section 5.10.10. on
page 106) it’s not possible to suppress an interrupt by
changing priority.
5.10.7.Interrupt Registers
115: 1F20
116: IRC
117: Interrupt Control Register
A zero in the flag IRC.DINT of register IRC prevents
the Interrupt Controller from pulling the signal NMI
Low. However, if this flag is set after the falling edge of
NMI, the corresponding interrupt cannot be cancelled.
bit
7
x
x
6
x
x
5
x
x
4
3
2
1
0
r
w
x
DAINT
DINT
DINT
1
x
x
RESET DAINT
A1INT CLEAR
reset
x
1
x
x
RESET
w1:
Reset
No action.
5.10.6.Precautions
w0:
Momentary reset of the Interrupt Control-
ler, all internal registers are cleared.
The write access to the IRRET must be performed just
before the RTI command at the end of the interrupt
service routine. After a write access to this location it is
guaranteed that the next command (should be RTI) will
be processed completely before a new interrupt
request is signaled to the CPU. If the RTI command
does not immediately follow the write to IRRET, an
interrupt with the same priority may be detected before
the corresponding RTI is processed. A stack underflow
may occur because this may happen several times.
The reset of the Interrupt Controller happens with writ-
ing zero to this flag. It is not necessary to write a one to
finish the reset.
The standard interrupt controller function is performed
by setting all flags to one. A hardware reset of the
Interrupt Controller is performed by setting the RESET
flag to Low and the other flags to High.
If an opcode fetch of a disable interrupt instruction (DI)
happens one clock cycle after the falling edge of NMI
(see Section 5.10.10. on page 106), it is possible, that
an interrupt service routine (ISR) is active, though the
corresponding interrupt is disabled. That is why after
disabling an interrupt, and before accessing critical
data, at least one uncritical instruction is necessary.
This guarantees that the ISR is finished before critical
data access and no further ISR can interrupt it.
DAINT
r1:
r0:
w1:
w0:
Disable after interrupt
Don’t disable after interrupt.
Disable Interrupt Controller after interrupt.
Cancel this feature.
Disable Interrupt Controller after interrupt.
This is the enable flag for the flag A1INT function.
DINT
r1:
r0:
Disable interrupt
Because it is now possible that an ISR can lengthen
the time between DI and enable interrupt (EI) indefi-
nitely, it is necessary that an ISR first saves registers
and enables interrupt flags, and then enables inter-
rupts. After interrupt execution, enable flags and regis-
ters must be restored. This guarantees, that other
interrupts are not locked out during interrupt execution.
Interrupts are enabled.
All interrupts are disabled.
Enable interrupts according to priority set-
ting.
w1:
w0:
Disable all interrupts.
A1INT
w1:
Allow one interrupt
No action.
w0:
Serve one interrupt.
This is a momentary signal. With DAINT = 0, only one
interrupt (with the highest priority) will be served.
Save Registers
Execute Interrupt
Restore Registers
Write to IRRET
RTI
The Flags DAINT and A1INT must be considered in
common. They provide the possibility to serve inter-
rupts one by one, only when the main program has
enough time.
CLEAR
w1:
Clear all requests
No action.
w0:
Momentarily clears all interrupt requests.
Fig. 5–11: Interrupt service routine
Micronas
101
MICRONAS [ MICRONAS ]
