VCT 38xxA
ADVANCE INFORMATION
5.14.2.Initialization
5.14.3.1. Operation of Subunit
For a proper setup the SW has to program the follow-
ing SU control bits in registers CCxI and CCxM: Inter-
rupt Mask (MSK), Force Output Logic (FOL, 0 recom-
mended), Output Action mode (OAM), Input Action
mode (IAM), Reset Capture register (RCR, 0 recom-
mended), and Lock After Capture (LAC). Refer to sec-
tion 5.14.5. for details.
After system reset the CCC and all SUs are in standby
mode (inactive).
In standby mode, the CCC is reset to value 0000h.
Capture and compare registers CCx are reset. No
information processing will take place, e.g. update of
interrupt flags. However, the values of registers CCxI
and CCxM are only reset by system reset, not by
standby mode. Thus, it is possible to program all mode
bits in standby mode and a predetermined start-up out
of standby mode is guaranteed.
Each SU is able to capture the CCC value at a point of
time given by an external input event processed by an
Input Action Logic.
Prior to entering active mode, proper SW configuration
of the Ports assigned to function as Input Capture
inputs and Output Action outputs has to be made. The
Output Action ports have to be configured as Special
Out and the Input Capture ports as special in (see
Section 5.18. on page 126).
A SU can also change an output line level via an Out-
put Action Logic at a point of time given by the CCC
value.
Thus, a SU contains a 16-bit capture register CCx to
store the input event CCC value, a 16-bit compare reg-
ister CCx to program the Output Action CCC value, an
8-bit interrupt register CCxI and an 8-bit mode register
CCxM. Two types of interrupts per SU enable interac-
tion with SW.
Please note, that the compare register CCx is reset in
standby mode. It can only be programmed in active
mode.
For limitations on operating the CAPCOM module in
CPU Slow mode, see section 5.14.3.1.15. on
page 117.
5.14.3.Operation of CCC
For entering active mode of the entire CAPCOM mod-
ule set, the enable bit in the standby register.
5.14.3.1.13. Compare and Output Action
The CCC will immediately start up-counting with the
selected clock frequency and will deliver this 16-bit
value to the SUs.
To activate a SUs compare logic the respective 16-bit
compare register CCx has to be programmed, Low
byte first. The compare action will be locked until the
High byte write is completed. As soon as CCx setting
and CCC value match, the following actions are trig-
gered:
The state of the counter is readable by reading the 16-
bit register CCC, Low byte first. Upon reading the Low
byte, the High byte is saved to a temporary latch,
which is then accessed during the subsequent High
byte read. Thus, for time stamp applications, read con-
sistency between Low and High byte is guaranteed.
– The flag CMP in the CCxI register is set.
– The CCxCOMP interrupt source is triggered.
The CCC is free running and will overflow from time to
time. This will cause generation of an overflow inter-
rupt event. The interrupt (CCCOFL) is directly fed to
the Interrupt Controller and also to all SUs where fur-
ther processing takes place.
– The CCxOR interrupt source is triggered when acti-
vated.
– The Output Action logic is triggered.
Four different reactions are selectable for the Output
Action signal: according to field CCxM.OAM (Table
5–17) the equal state will lead to a High or Low
level, or toggling or inactivity on this output.
Another means to control the Output Action is bit
CCxM.FOL. E.g. rise-mode and force will set the
output pin to High level, fall-mode and force to Low
level. This forcing is static, i.e. it will be permanently
active and may override compare events. Thus, it is
recommended to set and reset shortly after that, i.e.
to pulse the bit with SW. Toggle mode of the Output
Action logic and forcing leads to a burst with clock-
frequency and is not recommended.
116
Micronas
MICRONAS [ MICRONAS ]
