VCT 38xxA
ADVANCE INFORMATION
5.13.3.Timer Registers
208: 1F4E
211: 1F4C
209: TIM0L
212: TIM1L
210: Timer 0 Low Byte
213: Timer 1 Low Byte
bit
7
6
5
4
3
2
1
0
1
r
Read Low Byte of down-counter and latch High Byte.
Write Low Byte of reload value and reload down-counter.
w
reset
1
1
1
1
1
1
1
214: 1F4F
217: 1F4D
215: TIM0H
218: TIM1H
216: Timer 0 High Byte
219: Timer 1 High Byte
bit
7
6
5
4
3
2
1
0
1
r
Read latched High Byte of down-counter.
Write High Byte of reload value.
w
reset
1
1
1
1
1
1
1
TIMx have to be read Low byte first and written High
byte first.
220: 1F11
223: 1F13
221: TIM0M
224: TIM1M
222: Timer 0 Mode
225: Timer 1 Mode
bit
7
6
5
4
0
3
2
1
0
0
r/w
CSF
reset
0
0
0
0
0
0
CSF
r/w:
Clock Selection Field
Source of timer clock (see Table 5–12)
Table 5–12: CSF usage
CSF
Clock
Divider
Timer
Clock
Timer
Increment
Timer
Period
1
00
01
1x
f
f
f
/2
/2
/2
5.0625 MHz
19.775 KHz
77.248 Hz
197.53 ns
50.568 µs
12.945 ms
12.945 ms
3.3140 s
848.39 s
OSC
OSC
OSC
9
17
114
Micronas
MICRONAS [ MICRONAS ]
