ADVANCE INFORMATION
VCT 38xxA
2.12.Synchronization and Deflection
2.12.3.Horizontal Phase Adjustment
The synchronization and deflection processing is dis-
tributed over front-end and back-end. The video
clamping, horizontal and vertical sync separation and
all video related timing information are processed in
the front-end. Most of the processing that runs at the
horizontal frequency is programmed on the internal
Fast Processor (FP). Also the values for vertical and
East/West deflection are calculated by the FP soft-
ware.
This section describes a simple way to align PLL
phases and the horizontal frame position.
1. With HDRV the duration of the horizontal drive pulse
has to be adjusted
2. With POFS2 the delay between input video and dis-
play timing (e.g. clamping pulse for analog RGB)
has to be adjusted
3. With CSYDEL the delay between video and analog
RGB (OSD) has to be adjusted.
The generation of horizontal and vertical drive signals
can be synchronized to the video timing extracted in
the front-end or to a free running line counter in the
back-end.
4. With CSYDEL and HPOS the horizontal position of
both, the digital and analog RGB signal (from
SCART) relative to the clamping pulse has to be
adjusted to the correct position, e.g. the pedestal of
the generator signal.
2.12.1.Deflection Processing
5. With POFS3 the position of horizontal drive/flyback
relative to RGB has to be adjusted
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2–24). This block
contains two phase-locked loops:
6. With NEWLIN the position of a scaled video picture
can be adjusted (left, middle, center, etc; versions
with panorama scaler only).
– PLL2 generates the horizontal and vertical timing,
e.g. blanking, clamping and composite sync. Phase
and frequency are synchronized by the front sync
signal.
7. With HBST and HBSO, the start and stop values for
the horizontal blanking have to be adjusted.
Note: The processing delay of the internal digital video
path differs depending on the comb filter option of the
VCT 38xxA. The versions with comb filter have an
additional delay of 34 clock cycles.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal out-
put stage. Phase and frequency are synchronized
by the oscillator signal of PLL2.
The horizontal drive circuitry uses a digital sine wave
generator to produce the exact (subclock) timing for
the drive pulse HOUT. The generator runs at 1 MHz.
Under control of the EHPLL bit and the internal voltage
supervision it is either synchronized by the deflection
PLL or it is free running. In the output stage the fre-
quency is divided down to give drive-pulse period and
width. The drive pulse width is programmable. The
horizontal drive uses an open drain output transistor.
After power on or during reset the HOUT generation is
switched to a free running mode with a fix duty cycle of
50 %. For normal operation the EHPLL bit has to be
set first. During the switch the actual period of HOUT
can vary by up to 1 µs.
2.12.2.Angle and Bow Correction
The Angle and Bow correction is part of the horizontal
drive PLL. This feature allows a shift of the horizontal
drive pulse phase depending on the vertical position
on the screen. The phase correction has a linear
(angle) and a quadratic term (bow).
Micronas
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