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VCT3801A 参数 Datasheet PDF下载

VCT3801A图片预览
型号: VCT3801A
PDF下载: 下载PDF文件 查看货源
内容描述: 视频/控制/图文电视IC系列 [Video/Controller/Teletext IC Family]
分类和应用: 电视
文件页数/大小: 172 页 / 2219 K
品牌: MICRONAS [ MICRONAS ]
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VCT 38xxA  
ADVANCE INFORMATION  
2.15.I2C Bus Slave Interface  
Fig. 2–26 shows I2C bus protocols for read and write  
operations of the interface; the read operation requires  
an extra start condition and repetition of the chip  
address with read command set.  
Communication between the VDP and the TV control-  
ler is done via I2C bus. For detailed information on the  
I2C bus please refer to the Philips manual ‘I2C bus  
Specification’.  
2.15.1.Control and Status Registers  
The VDP has two I2C bus slave interfaces (for compat-  
ibility with VPC/DDP applications) one in the  
front-end and one in the back-end. Both I2C bus inter-  
faces use I2C clock synchronization to slow down the  
interface if required. Both I2C bus interfaces use one  
level of subaddress: the I2C bus chip address is used  
to address the VDP and a subaddress selects one of  
the internal registers. The I2C bus chip addresses are  
given below:  
Table 2–3 gives definitions of the VDP control and sta-  
tus registers. The number of bits indicated for each  
register in the table is the number of bits implemented  
in hardware, i.e. a 9-bit register must always be  
accessed using two data bytes but the 7 MSB will be  
‘don’t care’ on write operations and ‘0’ on read opera-  
tions. Write registers that can be read back are indi-  
cated in Table 2–3.  
Functions implemented by software in the on-chip con-  
trol microprocessor (FP) are explained in Table 2–5.  
Table 2–2: I2C chip addresses  
A hardware reset initializes all control registers to 0.  
The automatic chip initialization loads a selected set of  
registers with the default values given in Table 2–3.  
Chip  
Address  
A6 A5  
A4  
A3  
A2  
A1  
A0 R/W  
front-end  
back-end  
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1/0  
1/0  
The register modes given in Table 2–3 are  
– w:  
write only register  
– w/r: write/read data register  
The registers of the VDP have 8 or 16-bit data size;  
16-bit registers are accessed by reading/writing two  
8-bit data words.  
– r:  
– v:  
– h:  
read data from VDP  
register is latched with vertical sync  
register is latched with horizontal  
I2C write access  
subaddress 7c  
S
S
1000 111 W Ack  
1000 111 W Ack  
0111 1100  
0111 1100  
Ack 1 or 2 byte Data  
P
I2C read access  
subaddress 7c  
Ack S  
1000 111  
R
high byte Data  
Ack  
low byte Data Nak P  
W
R
Ack  
Nak  
S
=
=
=
=
=
=
0
1
0
1
Start  
Stop  
1
0
SDA  
SCL  
S
P
P
Fig. 2–26: I2C bus protocols  
32  
Micronas  
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