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VCT3801A 参数 Datasheet PDF下载

VCT3801A图片预览
型号: VCT3801A
PDF下载: 下载PDF文件 查看货源
内容描述: 视频/控制/图文电视IC系列 [Video/Controller/Teletext IC Family]
分类和应用: 电视
文件页数/大小: 172 页 / 2219 K
品牌: MICRONAS [ MICRONAS ]
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ADVANCE INFORMATION  
VCT 38xxA  
Table 2–3: I2C control and status registers of the video front-end  
2
I C Sub  
Number  
Mode  
Function  
Default Name  
address of bits  
FP Interface  
h’35  
8
r
FP status  
bit [0]  
bit [1]  
FPSTA  
write request  
read request  
busy  
bit [2]  
h’36  
h’37  
h’38  
16  
16  
16  
w
w
bit[8:0]  
bit[11:9]  
9-bit FP read address  
reserved, set to zero  
FPRD  
FPWR  
FPDAT  
bit[8:0]  
bit[11:9]  
9-bit FP write address  
reserved, set to zero  
w/r  
bit[11:0]  
FP data register, reading/writing to this  
register will autoincrement the FP read/  
write address. Only 16 bit of data are  
transferred per I2C telegram.  
Black Line Detector  
h’12  
16  
r
read only register, do not write to this register!  
after reading, LOWLIN and UPLIN are reset to 127 to start a  
new measurement  
BLKLIN  
bit[6:0]  
bit[7]  
number of lower black lines  
always 0  
LOWLIN  
bit[14:8]  
bit[15]  
number of upper black lines  
normal/black picture  
UPLIN  
BLKPIC  
Miscellaneous  
h’29  
16  
w/r  
Test pattern generator:  
TPG  
0
bit[10:0]  
bit[11]  
reserved (set to 0)  
disable/enable test pattern generator  
output mode:  
0/1  
0
0
TPGEN  
bit[13:12]  
TPGMODE  
00  
01  
10  
11  
Y/C = ramp (240 ... 17)  
Y/C = 16  
Y/C = 90  
Y/C = 240  
bit[15:14] 0/1  
reserved (set to 0)  
0
0
h’22  
16  
w/r  
NEWLINE (available for versions with panorama scaler only):  
bit[10:0]  
NEWLIN  
NEWLINE register  
This register defines the readout start of  
the next line in respect to the value of the  
sync counter.  
bit [15:11]  
reserved (set to 0)  
Micronas  
33  
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