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SDA9410-B13 参数 Datasheet PDF下载

SDA9410-B13图片预览
型号: SDA9410-B13
PDF下载: 下载PDF文件 查看货源
内容描述: 显示处理器,并采用扫描率转换器的嵌入式DRAM技术单位 [Display Processor and Scan Rate Converter using Embedded DRAM Technology Units]
分类和应用: 转换器动态存储器
文件页数/大小: 179 页 / 3137 K
品牌: MICRONAS [ MICRONAS ]
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SDA9410  
5.2  
Preliminary Data Sheet  
Input sync controller (ISCM/ISCS)  
Input sync controller (ISCM/ISCS)  
Signals  
Pin number  
Description  
HINM  
27  
horizontal synchronization signal (polarity programmable, I²C Bus  
parameter 11h HINPOLM, default: high active)  
VINM  
26  
28  
77  
78  
76  
vertical synchronization signal (polarity programmable, I²C Bus  
parameter 11h VINPOLM, default: high active)  
SYNCENM  
HINS  
enable signal for HINM and VINM signal, low active ("Input format  
conversion (IFCM/IFCS)" on page 26)  
horizontal synchronization signal (polarity programmable, I²C Bus  
parameter 33h HINPOLS, default: high active)  
VINS  
vertical synchronization signal (polarity programmable, I²C Bus  
parameter 33h VINPOLS, default: high active)  
SYNCENS  
enable signal for HINS and VINS signal, low active ("Input format  
conversion (IFCM/IFCS)" on page 26)  
Table 2  
Input signals  
The input sync controller derives framing signals from the H- and V-Sync for the input  
data processing. The framing signals depend on different I²C Bus parameters and mark  
the active picture area.  
HINM  
pixels per line  
VINM  
NALIPM + PD  
(ALPFIPM*2)  
lines  
per  
field  
(APPLIPM*8)*CLKM  
(NAPIPDLM*4 +  
NAPIPPHM+PD)*  
CLKM  
PD - Processing Delay  
Figure 7  
Input I²C Bus parameter  
The distance between the incoming H-syncs in system clocks of CLKM/CLKS must be  
even.  
22  
Micronas  
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