SDA9410
Preliminary Data Sheet
Block diagram
3
Block diagram
X2
X1/CLKD
TEST RESET
HINM
VINM
ISCM
clock
Input sync controller Master
doubling
PLLD
CLKOUT
SYNCENM
VM
Vector
memory
LBD
Letter
INTERLACED
HOUT
OSCM/S
Output sync
controller
Master
clock
box
doubling
PLLM
CLKM
ME
VOUT
detection
motion
BLANK
LM
estimation
Line memory
TSNR
VHCOMM
Vertical and
horizontal
ED
eDRAM
+
IFCM
YINM
Temporal,
spatial
SRCM
Scan rate
conversion
Master
LM
Line
Input
format
compression/
expansion
memory
noise
OFC
UVINM
conversion
Buffer
+
DAC
DAC
DAC
YO
UO
reduction
M
DLTI
DCTI
4:4:4
8:8:8
U
X
Voltage
control
+
Vertical
Peaking
Framing
Delay
VHCOMS
Vertical and
horizontal
IFCS
Input
expansion
YINS
VO
format
SRCS
Test-
controller
compression/
expansion
UVINS
conversion
LM
Line memory
clock
CLKS
doubling
PLLS
I²C
MC
HINS
VINS
ISCS
Input sync controller Slave
Memory
Controller
SYNCENS
SDA
SCL
Figure 1
Block diagram
The SDA 9410 contains the blocks, which will be briefly described below:
ISCM/S - Flexible input sync controller
IFCM/S - Input format conversion, Adjustable delay
VHCOMM/S - Vertical and horizontal compression, horizontal expansion, panorama mode (only M)
TSNR - Temporal and spatial noise reduction, noise measurement
LBD - Letter box detection
ME - Motion estimation, Film mode and phase detection
MC - Memory controller
OSCM/S - Flexible output sync controller
OFC - Output format conversion, 4:4:4, 8:8:8 interpolation, Adjustable delay
SRCM/S - Scan rate conversion, vertical expansion
MUX - Combination of the two output channels
DLTI/DCTI/Peaking - Luminance and chrominance transition improvement, luminance peaking
I2C - I²C bus interface
PLLM/S/D - PLL for frequency doubling
LM - Line memory core, VM - Vector memory core
ED - eDRAM core
14
Micronas
MICRONAS [ MICRONAS ]
