SDA9410
Preliminary Data Sheet
Pin Description
Table 1
Symbol
Pin definitions and functions
Pin
Input Function
Outp.
Num.
VSSLx *)
8,13,15,16,
22,23,75
S
Supply voltage for digital logic parts ( VSS = 0 V )
VDDLx
VSSPx
9,12, 68,74
S
S
Supply voltage for digital logic parts ( VDD = 3.3 V )
10,17,29,43,
57, 70, 79,
100
Supply voltage for pads ( VSS = 0 V )
Supply voltage for pads ( VDD = 3.3 V )
VDDPx
11,21,36,54,
69, 80,99
S
VSSE1
VDDEx
VSSAx
67
S
S
S
Supply voltage for embedded DRAM ( VSS = 0 V )
14,66
Supply voltage for embedded DRAM ( VDD = 3.3 V )
Supply voltage for analog PLL and for analog parts DAC ( VSS = 0 V )
19,59,92,96,
98
VDDAx
20,60, 95,97
S
Supply voltage for analog PLL and for analog parts DAC
( VDD = 3.3 V )
YINM 0...7
UVINM 0...7
YINS 0...7
UVINS 0...7
RESET
39,...,42;
44,...,47
I/TTL
Data input Y master channel
30,...,35;
37; 38
I/TTL PD Data input UV master channel
I/TTL PD Data input Y slave channel
I/TTL PD Data input UV slave channel
61,...,65;
71,...,73
48,..,53;
55;56
81
I/TTL
System reset. The RESET input is low active. In order to ensure
correct operation a "Power On Reset" must be performed. The
RESET pulse must have a minimum duration of two clock periods of
the master (CLKM) and slave clock (CLKS), respectively.
HINM
VINM
27
26
I/TTL
PD
H-Sync input master channel
I/TTL
PD
V-Sync input master channel
SYNCENM
HINS
28
77
I/TTL
Synchronization enable input master channel
H-Sync input slave channel
I/TTL
PD
VINS
78
I/TTL
PD
V-Sync input slave channel
SYNCENS
SDA
76
24
25
7
I/TTL
IO
Synchronization enable input slave channel
I2C-Bus data line
SCL
I
I2C-Bus clock line
BLANK
VOUT
HOUT
O/TTL
O/TTL
O/TTL
Blanking signal
5
V-Sync output
4
H-Sync output
17
Micronas
MICRONAS [ MICRONAS ]
