SDA 9380 - B21
Preliminary Data Sheet
System description
5.3
Reset modes
The circuit is only completely reset at power-on/off (timing diagram ref. 11.3). If the pin RESN has L-
level or during standby operation some parts of the circuit are not affected (timing diagram ref. 11.4):
External Reset
(pin RESN=0)
Standby mode
Power-On-Reset
(I2C bit STDBY=1)
HD output
High
inactive
active
active
active
active
H-protection
V-protection
inactive
active1)
active1)
IIC-Interface (SDA, SCL)
IIC-Register 01..1C
IIC-Register 00, 1D...30h
Status bit PONRES
VREFH
tristate
ready
ready
set to default values
set to default values
set to 12)
set to default values
not affected
set to 1
set to default values
not affected
not affected
inactive
not affected
inactive
not affected
inactive
CPU
inactive
1): inactive if HPROT < V2 (typ. 1.5V)
2): can only be read after Power-On-Reset is finished
Note: Power-On-Reset state is deactivated after ca. 32768 cycles of the X1/X2 oscillator clock.
RESN=Low and standby state are deactivated after ca. 42 cycles of the CLL clock.
5.4
Frequency ranges
H
V
n
L
15.625 kHz
15.75 kHz
18.75 kHz*
31.25 kHz
50 Hz
60 Hz
60 Hz
625 I
525 I
625 I
50 Hz
100 Hz
625 NI / 1250 I
625 I
31.5 kHz
60 Hz
70 Hz
525 NI / 1050 I
449 NI
120 Hz
525 I
33.75 kHz*
35 kHz*
60 Hz
1125 I
525 NI
66.7 Hz
38 kHz*
60 Hz
72 Hz
632 NI
525 NI
*) only with internal clock generation
The allowed deviation of all input line frequencies is max. ±4.5%.
n : number of lines per frame
L
Micronas
5-13
2001-01-29
MICRONAS [ MICRONAS ]
