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SDA9380-B21 参数 Datasheet PDF下载

SDA9380-B21图片预览
型号: SDA9380-B21
PDF下载: 下载PDF文件 查看货源
内容描述: EDDC增强偏转器和RGB处理器 [EDDC Enhanced Deflection Controller and RGB Processor]
分类和应用: 商用集成电路
文件页数/大小: 72 页 / 404 K
品牌: MICRONAS [ MICRONAS ]
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SDA 9380 - B21  
Preliminary Data Sheet  
System description  
5.2  
Circuit description  
The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase locked to  
the incoming horizontal sync pulse and exactly 864 times faster than the horizontal frequency. The  
polarity of the external horizontal sync pulses may be positive (see figure below) or negative. In  
case of negative polarity the incoming HSYNC signal is automatically inverted for an easier applica-  
tion in VGA or SVGA mode.  
V
V
HSmax  
V
HSpp  
HSmin  
t
W
Incoming signal HSYNC (internal clock)  
2
Pulse width t for I C-bus Bit ’HSWMI’=0:  
w
1.5 µs ... 4.5µs (High or Low level)  
3.0 µs ... 9.0µs (High or Low level)  
FH1_2 = High  
FH1_2 = Low  
2
Pulse width t for I C-bus Bit ’HSWMI’=1:  
w
0.8 µs ... 4.5µs (High or Low level)  
1.7 µs ... 9.0µs (High or Low level)  
FH1_2 = High  
FH1_2 = Low  
(The specified pulse width depends on the I²C-bus bits INCR4...INCR0 rsp. PLL clock frequency.  
The above values are valid for INCR = 6. For higher INCR values the allowed pulse width is  
decreasing proportional to the increasing PLL clock frequency.)  
The described input signal is first applied to an A/D converter. Conversion takes place with 7 bits  
and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to obtaine defined slopes  
for further measurements (PAL/NTSC applications). In addition the actual high and low level of the  
signal as well as a threshold value is evaluated and used to calculate the phase error between inter-  
nal clock and external horizontal sync pulse. By means of digital PI filtering an increment is gained  
2
from this. The PI filter can be set by the I C-bus VCR bit so that the lock-in behaviour of the PLL is  
optimal in relation to either the TV or VCR mode. Moreover it is possible to adapt the nominal fre-  
2
quency by means of 5 I C-bus bits (INCR4..INCR0) to different horizontal frequencies. An additional  
bus bit GENMOD offers the possibility to use the PLL as a frequency generator which frequency is  
controlled by the INCR bits.  
Micronas  
5-11  
2001-01-29  
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