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SDA9380-B21 参数 Datasheet PDF下载

SDA9380-B21图片预览
型号: SDA9380-B21
PDF下载: 下载PDF文件 查看货源
内容描述: EDDC增强偏转器和RGB处理器 [EDDC Enhanced Deflection Controller and RGB Processor]
分类和应用: 商用集成电路
文件页数/大小: 72 页 / 404 K
品牌: MICRONAS [ MICRONAS ]
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SDA 9380 - B21  
Preliminary Data Sheet  
System description  
within 85ms to its final value. The high time is kept constant. The normal operating pulse ratio H/L is  
either 45/55 or 40/60 (selectable by I²C). A watch dog function limits an increasing of the HD period  
to max. +10%.  
2
The implemented Black Switch-Off behaviour is defined by two I C bits (BSO1, BSO0). When  
enabled the signal at BSOIN (e.g. the supply voltage of the line output stage) is watched. If its level  
does not come up to a defined threshold Black Swich-Off is started (see 11.2). At first the RGB out-  
puts are switched to continuous blanking immediately and the vertical output signals are changed to  
about 115..120% overscan. After a delay of 42 lines the picture tube capacitance is discharged with  
a current of some mA. From now the vertical overscan rate is calculated depending on the actual  
2
voltage at BSOIN to get the desired deflection angle. Three relations are selectable by I C. After the  
voltage at BSOIN is dropped down to about 20% of its initial value the output HD and the overscan  
calculation may stop.  
The protection circuit watches an EHT reference and the saw-tooth of the vertical output stage. If  
the EHT succeeds a defined threshold or if the V-deflection fails (refer to 11.5) the related bit is set in  
the status byte and the output PROTON goes High. The output HD is deactivated (H-level) immedi-  
ately independent of the selected Black Switch-Off function.  
HPROT:  
input V < V2  
continuous blanking  
HD disabled  
i
V > V1  
i
V2 =V < V1  
operating range  
i
VPROT:  
vertical saw-tooth voltage  
V < V1 in first half of V-period  
i
or V > V2 in second half : HD disabled  
i
The pin SCP delivers the composite blanking signal SCP. It contains burst (V ), H-blanking HBL  
b
(V  
) and selectable V-blanking (control bit SSC). The phase and width of the H-blanking period  
HBL  
2
can be varied by I C-Bus. For the timing following settings are possible :  
BD = 1  
: T = 0  
BL  
BD = 0, BSE = 0 (default value)  
BD = 0, BSE = 1(alignment range)  
: T  
: T  
: T  
= t (H-flyback time)  
HBL  
HBL  
DBL  
f
= (4 * H_blanking-time + 1) / CLL  
= (H_shift + 4 * H_blanking_phase  
- 2*H_blanking_time + 45) / CLL  
SSC = 0  
SSC = 1  
: T = T  
during V-blanking period  
BL  
VBL  
: T is always T  
BL  
HBL  
Micronas  
5-8  
2001-01-29  
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