SDA 9380 - B21
Preliminary Data Sheet
Pin configuration
4.1
Pin description
Name
Pin No.
Type Description
1
2
3
4
5
CLKI
I/TTL Input for external line locked clock *)
X2
X1
Q
I
Reference oscillator output, Crystal
Reference oscillator input, Crystal
CLEXT
TEST
I/TTL Switching between internal (L) and external clock (H) *)
I/TTL Switching between normal operation (TEST=L) and test mode
(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-
nal test pins)
6
SUBST
S
Substrate pin, has to be connected to ground whenever a
power supply or signal is applied
7
RESN
SCL
I/TTL Reset input, active Low
8
I
I²C Bus clock
9
SDA
IQ
S
I²C Bus data
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD(D)
VSS(D)
HD
Digital supply
S
Digital ground
Q
Control signal output for H driver stage (open drain)
H35K
Q/TTL Goes High when frequency of HSYNC is about 35kHz or more
Q/TTL Goes High when frequency of HSYNC is about 38kHz
Q/TTL Pulse width modulated control signal output
I/TTL V-sync input
H38K
PWM
VSYNC
FH1_2
HSYNC
VDD(A1)
VSS(A1)
Φ2
VDD(A2)
VSS(A2)
E/W
I/TTL Switching between 1fH mode (L) and 2fH mode (H)
I
HSYNC input (CLEXT=H: TTL; CLEXT=L: analog) *)
Analog supply
S
S
I
Analog ground
Line flyback for H-delay compensation
Analog supply
S
S
Q
Q
Q
Q
S
S
I
Analog ground
Control signal output for East-West raster correction
Output of an I²C Bus controlled DC voltage
Control signal output for DC coupled V-output stage
Like VD+
D/A
VD+
VD-
VDD(A3)
VSS(A3)
VPROT
Analog supply
Analog ground
Watching external V-output stage (input is the V-saw-tooth from
feedback resistor)
31
32
33
34
HPROT
HSAFE
BSOIN
IBEAM
I
I
I
I
Watching EHT (input is e.g. H-flyback)
Watching B+ when frequency of HD has to be decreased
Input for starting Black Switch-Off
Input for a beam current dependent signal for stabilization of
width, height and H-phase
35
PROTON
Q/TTL Protection on (goes High after response of H- or V-protection)
Micronas
4-5
2001-01-29
MICRONAS [ MICRONAS ]
