SDA 9380 - B21
Preliminary Data Sheet
Pin configuration
Pin No.
36
Name
Type Description
VREFH
IQ
Reference voltage
37
VBLO
VREFN
VREFC
DCI
Q/TTL Vertical blanking output
38
IQ
I
Ground for VREFH
39
Reference current input
40
I
Dark current input for cut off and white level control
Analog supply
41
VDD(A4)
Y/R 0
U/G 0
V/B 0
VSS(A4)
R/Y 1
G/U 1
B/V 1
FBL1
S
I
42
Luminance or R input
43
I
U signal or G input
44
I
V signal or B input
45
S
I
Analog ground
46
First R or Y input for insertion
First G or U input for insertion
First B or V input for insertion
Fast blanking input for RGB1
Fast blanking input for RGB2
Second R input for insertion
Second G input for insertion
Second B input for insertion
Analog supply for RGB output stage
R output
47
I
48
I
49
I
50
FBL2
I
51
R2
I
52
G2
I
53
B2
I
54
VDD(MC)
ROUT
GOUT
BOUT
SCP
S
Q
Q
Q
Q
55
56
G output
57
B output
58
Blanking signal with H- and color burst component
(V-component selectable by I²C Bus)
59
60
61
62
63
64
VSS(MC)
SVM
S
Q
S
S
Analog ground for RGB output stage
Luminance output for scan velocity modulation circuit
Digital supply
VDD(D)
VSS(D)
SSD
Digital ground
I/TTL Disables softstart
SWITCH
Q/TTL Output of an I²C Bus controlled switch (register 00, bit SW)
*) The external clock mode can not be used with 18.75, 33.75kHz, 35kHz and 38kHz line frequency.
Micronas
4-6
2001-01-29
MICRONAS [ MICRONAS ]
