MSP 34x0D
PRELIMINARY DATA SHEET
Table 5–3: Control Register (Subaddress: 00 hex)
Name
Subaddress
MSB
14
13..1
LSB
CONTROL
00 hex
1 : RESET
0 : normal
0
0
0
5.1. Protocol Description
Write to DSP or Demodulator
S
write
device
address
Wait
ACK
subaddr
ACK
addr byte
high
ACK
addr byte
low
ACK
data byte
high
ACK
data byte
low
ACK
P
Read from DSP or Demodulator
S
write
device
address
Wait ACK
subaddr
ACK addr byte ACK addr byte ACK
high low
S
read
device
address
Wait
ACK data byte ACK data byte NAK
high low
P
Write to Control or Test Registers
S
write
device
address
Wait ACK
subaddr
ACK
data byte high
ACK
data byte low
ACK
P
Note: S =
I2C bus Start Condition from master
I2C bus Stop Condition from master
P =
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (=MSP, gray)
or master (=CCU, hatched)
NAK = Not-Acknowledge Bit: HIGH on I2C_DA from master (=CCU, hatched) to indicate ‘End of Read’
or from MSP indicating internal error state
Wait = I2C clock line held low by the slave (=MSP) while interrupt is serviced (<1.8 ms)
1
0
I2C_DA
S
P
I2C_CL
Fig. 5–1: I2C bus protocol
(MSB first; data must be stable while clock is high)
18
Micronas
MICRONAS [ MICRONAS ]
