PRELIMINARY DATA SHEET
MSP 34x0D
5. I2C Bus Interface: Device and Subaddresses
Due to the internal architecture of the MSP 34x0D, the
IC cannot react immediately to an I2C request. The typ-
ical response time is about 0.3 ms for the DSP proces-
sor part and 1 ms for the demodulator part if NICAM
processing is active. If the receiver (MSP) can’t receive
another complete byte of data until it has performed
some other function; for example, servicing an internal
interrupt, it can hold the clock line I2C_CL LOW to
force the transmitter into a wait state. The positions
within a transmission where this may happen are indi-
cated by ’Wait’ in section 5.1. The maximum wait
period of the MSP during normal operation mode is
less than 1 ms.
As a slave receiver, the MSP 34x0D can be controlled
via I2C bus. Access to internal memory locations is
achieved by subaddressing. The demodulator and the
DSP processor parts have two separate subaddress-
ing register banks.
In order to allow for more MSP 34x0D ICs to be con-
nected to the control bus, an ADR_SEL pin has been
implemented. With ADR_SEL pulled to HIGH, LOW, or
left open, the MSP 34x0D responds to changed device
addresses. Thus, three identical devices can be
selected.
I2C bus error caused by MSP hardware problems:
In case of any internal error, the MSPs wait period is
extended to 1.8 ms. Afterwards, the MSP does not
acknowledge (NAK) the device address. The data line
will be left HIGH by the MSP and the clock line will be
released. The master can then generate a STOP con-
dition to abort the transfer.
By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.
The IC is selected by asserting a special device
address in the address part of an I2C transmission. A
device address pair is defined as a write address (80,
84, or 88hex) and a read address (81, 85, or 89hex
)
(see Table 5–1). Writing is done by sending the device
write address, followed by the subaddress byte, two
address bytes, and two data bytes. Reading is done by
sending the device write address, followed by the sub-
address byte and two address bytes. Without sending
a stop condition, reading of the addressed data is com-
pleted by sending the device read address (81, 85, or
89hex) and reading two bytes of data (see Fig. 5–1:
“I2C Bus Protocol” and section 5.2. “Proposal for
MSP 34x0D I2C Telegrams”).
By means of NAK, the master is able to recognize the
error state and to reset the IC via I2C bus. While trans-
mitting the reset protocol (see section 5.2.4. on page
19) to ‘CONTROL’, the master must ignore the not-
acknowledge bits (NAK) of the MSP.
A general timing diagram of the I2C Bus is shown in
Fig. 5–2 on page 19.
Table 5–1: I2C Bus Device Addresses
ADR_SEL
Low
Read
81 hex
High
Read
85 hex
Left Open
Read
89 hex
Mode
Write
Write
Write
MSP device address
80 hex
84 hex
88 hex
Table 5–2: I2C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
W
Function
CONTROL
TEST
0000 0000
0000 0001
0001 0000
0001 0001
0001 0010
0001 0011
00
01
10
11
12
13
software reset
W
only for internal use
WR_DEM
RD_DEM
WR_DSP
RD_DSP
W
write address demodulator
read address demodulator
write address DSP
W
W
W
read address DSP
Micronas
17
MICRONAS [ MICRONAS ]
