MSP 34x0D
PRELIMINARY DATA SHEET
4.7. I2S Bus Interface
The I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2:
By means of this standardized interface, additional
feature processors can be connected to the
MSP 34x0D. Two possible formats are supported: The
standard mode (MODE_REG[4]=0) selects the SONY
format, where the I2S_WS signal changes at the word
boundaries. The so-called PHILIPS format, which is
characterized by a change of the I2S_WS signal one
I2S_CL period before the word boundaries, is selected
by setting MODE_REG[4]=1.
For input, four channels (two channels per line,
2*16 bits) per sampling cycle (32 kHz) are transmit-
ted.
2. I2S_DA_OUT:
For output, two channels (2*16 bits) per sampling
cycle (32 kHz) are transmitted.
3. I2S_CL:
Gives the timing for the transmission of I2S serial
data (1.024 MHz).
The MSP 34x0D normally serves as the master on the
I2S interface. Here, the clock and word strobe lines are
4. I2S_WS:
driven
by
the
MSP 34x0D.
By
setting
The I2S_WS word strobe line defines the left and
right sample.
MODE_REG[3]=1, the MSP 34x0D is switched to a
slave mode. Now, these lines are input to the
MSP 34x0D and the master clock is synchronized to
576 times the I2S_WS rate (32 kHz). NICAM operation
is not possible in this mode.
A precise I2S timing diagram is shown in Fig. 4–6.
(Data: MSB first)
FI2SWS
I2S_WS
SONY Mode
SONY Mode
PHILIPS Mode
PHILIPS Mode
PHILIPS/SONY Mode programmable by MODE_REG[4]
Detail C
I2S_CL
Detail A
I2S_DAIN
R LSB L MSB
L LSB R MSB
R LSB L LSB
16 bit left channel
16 bit right channel
16 bit right channel
Detail B
I2S_DAOUT
R LSB L MSB
L LSB R MSB
R LSB L LSB
16 bit left channel
Detail C
Detail A,B
1/FI2SCL
I2S_CL
I2S_CL
TI2S1
TI2S2
TI2SWS1
TI2SWS2
I2S_WS as INPUT
I2S_DA_IN
TI2S3
TI2S4
TI2S5
TI2S6
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4–6: I2S bus timing diagram
16
Micronas
MICRONAS [ MICRONAS ]
