MSP 3400C
PRELIMINARY DATA SHEET
Table 5–3: Control Register
Name
15
RESET
14..0
CONTROL
0
5.1. Protocol Description
Write to DFP or Demodulator Part (long protocol)
S
daw
Wait ACK
sub-addr
ACK
addr-byte
high
ACK addr-byte low ACK data-byte high ACK data-byte low ACK
P
Read from DFP Part (long protocol)
S
daw
Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK
high low
S
dar
Wait ACK data-byte ACK data-byte NAK
P
high
low
Write to Control / Test / AGC / PLL_Cap Registers (short protocol)
S
daw
Wait ACK
sub-addr
ACK
data-byte high
ACK
data-byte low
ACK
NAK
P
P
Read from Control / Test / AGC / PLL_Cap Registers (short protocol)
S
daw
Wait ACK
sub-addr
ACK
S
dar
Wait ACK
data-byte high ACK
data-byte low
2
Note: S =
I C-Bus Start Condition from master
2
P =
I C-Bus Stop Condition from master
daw = Device Address Write
dar = Device Address Read
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSPC, grey)
or master (= CCU, hatched)
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate
‘End of Read’ or from MSPC indicating internal error state (not illustrated)
2
Wait = I C-Clock line held low by the slave (= MSPC) while interrupt is serviced (<1.77 ms)
1
0
I2C_DA
I2C_CL
S
P
2
(MSB first; data must be stable while clock is high)
Fig. 5–1: I C bus protocol
MICRONAS INTERMETALL
17
MICRONAS [ MICRONAS ]
