MSP 3400C
PRELIMINARY DATA SHEET
2
2
4.7. I S Bus Interface
The I S bus interface consists of five pins:
1. I2S_DA_IN1:
By means of this standardized interface, additional fea-
ture processors can be connected to the MSP 3400C.
Two possible formats are supported: The standard
mode (MODE_REG[4]=0) selects the SONY format,
where the I2S_WS signal changes at the word bound-
aries. The so-called PHILIPS format, which is character-
izedbyachangeoftheI2S_WSsignal, oneI2S_CLperi-
od before the word boundaries, is selected by setting
MODE_REG[4]=1.
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
2. I2S_DA_IN2:
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
3. I2S_DA_OUT:
For output, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
4. I2S_CL:
2
Gives the timing for the transmission of I S serial data
The MSP 3400C normally serves as the master on the
I S interface. Here, the clock and word strobe lines are
2
(1.024 MHz).
driven by the MSP 3400C. BysettingMODE_REG[3]=1,
the MSP 3400C is switched to a slave mode. Now, these
lines are input to the MSP 3400 C, and the master clock
is synchronized to 576 times the I2S_WS rate (32 kHz).
No D2MAC operation is possible in this mode.
5. I2S_WS:
The I2S_WS word strobe line defines the left and right
sample.
A detailed timing diagram is shown in Fig. 4–7.
(Data: MSB first)
F
I2SWS
2
I S_WS
SONY Mode
PHILIPS Mode
SONY Mode
PHILIPS Mode
PHILIPS/SONY Mode programmable by MODE_REG[4]
Detail C
2
I S_CL
Detail A
2
I S_DAIN
R LSB L MSB
L LSB R MSB
R LSB L LSB
16 bit left channel
16 bit left channel
16 bit right channel
16 bit right channel
Detail B
2
I S_DAOUT R LSB
L MSB
L LSB R MSB
R LSB L LSB
Detail C
Detail A,B
F
I2SCL
2
2
I S_CL
I S_CL
T
T
T
I2S2
I2S1
T
T
T
I2SWS1
I2SWS2
2
2
I S_WS as INPUT
I S_DA_IN
T
T
I2S3
I2S4
I2S5
I2S6
2
2
I S_WS as OUTPUT
I S_DA_OUT
2
Fig. 4–7: I S Bus timing diagram
MICRONAS INTERMETALL
15
MICRONAS [ MICRONAS ]
