MSP 3400C
PRELIMINARY DATA SHEET
6. Programming the Demodulator Part
6.1. Registers: Table and Addresses
In Table 6–1, all Write Registers are listed.
All transmissions on the control bus are 16 bits wide.
Data for the demodulator part has 8 or 12 significant bits.
These data have to be inserted LSB bound and filled
with zero bits into the 16 bit transmission word. If chan-
nel 1 or channel 2 is selected in the channel matrix while
any of the parameters are changed, the corresponding
output must be muted. Click and crack noise may occur
during coefficient changes. Table 4–1 explains how to
assign FM carriers to the MSPC-Sound IF channels and
the corresponding matrix modes in the audioprocessing
part.
Table 6–1: MSP 3400C demodulator write registers
Register
Protocol
Write
Function
Address
(hex)
AD_CV
long
long
00BB
input selection, configuration of AGC and Mute Function,
and selection of A/D-converter
MODE_REG
0083
mode register
FIR_REG_1
FIR_REG_2
long
long
0001
0005
serial shift register for 6 8 bit, filter coefficient channel 1 (48 bit)
serial shift register for 6 8 bit, + 2 12 bit off set (total 72 bit)
DCO1_LO
DCO1_HI
DCO2_LO
DCO2_HI
long
long
long
long
0093
009B
00A3
00AB
increment channel 1 Low Part
increment channel 1 High Part
increment channel 2 Low Part
increment channel 2 High Part
1)
PLL_CAP
short
1F
switchable PLL capacities
Table 6–2: MSP 3400C demodulator read registers
Register
Protocol
Read
Function
Address
(hex)
1)
PLL_CAP
short
short
long
1F
switchable PLL capacities
1)
AGC_RMS
1E
RMS value, comparable with reference value
C_AD_BITS
0023
A read from this address always responds with 0. This ensures
software compatibility with the MSP 3410 readout. Reading 0 from
this register signals “No NICAM”.
1)
The registers PLL_CAP and AGC_RMS are only available in MSP 3400C. In MSP 3410 and MSP 34x0D, this register
cannot be accessed.
20
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
