MSP 3400C
PRELIMINARY DATA SHEET
2
2
5. I C Bus Interface: Device and Subaddresses
of data. Refer to Fig. 5–1 I C Bus Protocol and section
2
5.2. Proposal for MSP 3400C I C Telegrams.
As a slave receiver, the MSP 3400C can be controlled
via I C bus. Access to internal memory locations is
achieved by subaddressing. The demodulator part and
the audio processor part (DFP) have two separate sub-
addressing register banks.
2
Due to the internal architecture of the MSP 3400C, the
IC cannot react immediately to an I C request. The typi-
2
cal response time is about 0.3 ms. If the addressed pro-
2
cessor is not ready for further transmissions on the I C
bus, the clock line I2C_CL is pulled low. This puts the
current transmission into a wait state. After a certain pe-
riod of time, the MSP 3400C releases the clock, and the
interrupted transmission is carried on.
In order to allow for more MSP 3400C ICs to be con-
nected to the control bus, an ADR_SEL pin has been im-
plemented. With ADR_SEL pulled to high, the MSP
3400Crespondstochangeddeviceaddresses, thustwo
identical devices can be selected. Other devices of the
same family will have different subaddresses (e.g. 34x0)
2
The I C Bus lines can be set tristate by switching the IC
into “Standby”-mode.
2
I C-Bus error conditions:
By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.
In case of any internal error, the MSP’s wait-period is ex-
tended to 1.77 ms. Afterwards, the MSP does not ac-
knowledge (NAK) the device address. The data line will
be left HIGH by the MSP, and the clock line will be re-
leased. The master can then generate a STOPcondition
to abort the transfer.
The IC is selected by asserting a special device address
2
in the address part of an I C transmission. A device ad-
dress pair is defined as a write address (80 hex or 84
hex) and a read address (81 hex or 85 hex). Writing is
done by sending the device write address first, followed
by the subaddress byte, two address bytes, and two
data bytes. For reading, the read address has to be
transmitted first by sending the device write address (80
hexor84hex), followedbythesubaddressbyte, andtwo
address bytes. Without sending a stop condition, read-
ing of the addressed data is done by sending the device
read address (81 hex or 85 hex) and reading two bytes
By means of NAK, the master is able to recognize the er-
ror state and to reset the IC via I C-Bus. While transmit-
ting the reset protocol (section. 5.2.4.) to ‘CONTROL’,
the master must ignore the not acknowledge bits (NAK)
of the MSP.
2
A detailed timing diagram is shown in Fig. 5–1 and
Fig. 5–2.
2
Table 5–1: I C Bus Device Addresses
ADR_SEL
Low
High
Left Open
Read
89 hex
Mode
Write
Read
Write
Read
Write
MSP device address
80 hex
81 hex
84 hex
85 hex
88 hex
2
Table 5–2: I C Bus Device and Subaddresses
Name
Binary Value
0000 0000
0000 0001
0000 0010
0001 0000
0001 0001
0001 0010
0001 0011
0001 1110
0001 1111
Hex Value
Function
CONTROL
TEST1
00
01
02
10
11
12
13
1E
1F
software reset
only for internal use
only for internal use
write address demodulator
read address demodulator
write address DFP
read address DFP
read AGC RMS
TEST2
WR_DEM
RD_DEM
WR_DFP
RD_DFP
AGC
PLL_CAP
read / write PLL_Cap
16
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
