DATA SHEET
MAS 35x9F
T
SOCLK
H
SOC
L
H
SOI
L
T
T
SOISS
SOISS
H
SOD
L
T
SOODC
Fig. 4–23: Serial output interface timing
Vh
SOC
Vl
Vh
7
6 5 4 3 2 1 0
15 14 13 12 11 10
14
15
13 12 11 10
8
9
9
8
7 6 5 4 3 2 1 0
SOD
SOI
Vl
Vh
Vl
right 16-bit audio sample
left 16-bit audio sample
Fig. 4–24: Sample timing of the SDO interface in 16 bit/sample mode
D0:346 settings are
bit[14] = 0 (SOC not inverted)
bit[11] = 1 (SOI delay)
bit[5] = 0 (word strobe not inverted)
bit[4] = 1 (16 bits/sample)
Vh
...
...
SOC
Vl
Vh
SOD
SOI
...
31
30 29 28 27 26 25 ... 7
0
6 5 4 3 2 1 0
31 30 29 28 27 26 25
7
6
5
4
3
2
1
Vl
Vh
Vl
right 32-bit audio sample
left 32-bit audio sample
Fig. 4–25: Sample timing of the SDO interface in 32 bit/sample mode
D0:346 settings are
bit[14] = 0 (SOC not inverted)
bit[11] = 0 (no SOI delay)
bit[5] = 1 (word strobe inverted)
bit[4] = 0 (32 bits/sample)
Micronas
June 30, 2004; 6251-505-1DS
75
MICRONAS [ MICRONAS ]
