MAS 35x9F
DATA SHEET
Table 4–7: Allowed transmission delays of external data source MPEG1/2 Layer 2/3
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
tSTART48-320 Allowed delay time before
start of serial data
EOD
3.1
ms
ms
ms
ms
ms
ms
ms
ms
ms
48 kHz/s, 320 kbit/s
48 kHz/s, 64 kbit/s
24 kHz/s, 320 kbit/s
24 kHz/s, 32 kbit/s
12 kHz/s, 64 kbit/s
12 kHz/s, 16 kbit/s
8 kHz/s, 64 kbit/s
8 kHz/s, 8 kbit/s
tSTART48-64
tSTART24-320
tSTART24-32
tSTART12-64
tSTART12-16
tSTART8-64
tSTART8-8
5.7
transmission after assertion
of signal at EOD
4.2
9.2
23.1
25.6
34.8
38.4
1.3
tSTOP
Allowed delay time before
stop of serial data
Clock rate of input data
1 Mbit/s
EOD
transmission after
deassertion of signal at EOD
T
SICLK
H
SI(B)C
L
H
SI(B)I
L
T
T
T
SIIS
SIIH
H
SI(B)D
L
T
SIDH
SIDS
2
Fig. 4–22: Serial input of I S signal
4.6.2.3. Serial Output Interface Characteristics (SDO)
at T = T , V
, V
= 2.2 ... 3.6 V, f
= 18.432 MHz, Typ. values for T = 25 °C in P(L/M)QFP package
CRYSTAL A
A
SUPD SUPA
Limit Values
Symbol
Parameter
Pin Name
Unit
Test Conditions
Min.
Typ.
Max.
tSOCLK
tSOISS
tSOODC
I2S clock output frequency
SOC
325
ns
ns
ns
fS = 48 kHz Stereo
32 bits per sample
I2S word strobe delay time
after falling edge of clock
SOC,
SOI
0
0
I2S data delay time after
falling edge of clock
SOC,
SOD
74
June 30, 2004; 6251-505-1DS
Micronas
MICRONAS [ MICRONAS ]
