DATA SHEET
MAS 35x9F
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:349
Output Clock Configuration (affects pin CLKO) (reset = 80000
)
All
OutClkConfig
hex
bit[19]
CLKO configuration
0
output clock signal at CLKO
CLKO is tristate
1 (reset)
The CLKO output pin of the MAS 35x9F can be disabled via bit[19].
bit[18]
bit[17]
Reserved, must be set to zero
Additional division by 2 if scaler is on (bit[8] cleared)
0 (reset)
1
oversampling factor 512/768
oversampling factor 256/384
bit[16:9]
bit[8]
Reserved, must be set to zero
Output clock scaler
0 (reset)
1
set output clock according to audio sample rate
(see Table 2–1)
output clock fixed at 24.576 or 22.5792 MHz
For a list of output frequencies at pin CLKO please refer to Table 2–1.
bit[7:0] reserved, must be set to zero
Changes at this memory address must be validated by setting bit[0] of
D0:346.
D0:350
D0:351
Soft Mute
MPEG
SoftMute
%0 (reset) mute off
%1
mute on
S/PDIF channel status bits category code setting (reset = 8200 ) All
SpdOutBits
hex
Micronas
June 30, 2004; 6251-505-1DS
35
MICRONAS [ MICRONAS ]
