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MAS3549F 参数 Datasheet PDF下载

MAS3549F图片预览
型号: MAS3549F
PDF下载: 下载PDF文件 查看货源
内容描述: MAS 35x9F MPEG 2/3层, AAC音频解码器, G.729附录编解码器 [MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec]
分类和应用: 解码器编解码器
文件页数/大小: 92 页 / 1187 K
品牌: MICRONAS [ MICRONAS ]
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DATA SHEET  
MAS 35x9F  
Table 3–9: D0 control memory cells  
Memory  
Address  
(hex)  
Function  
Name  
D0:346  
Main I/O Control (reset = 8025  
)
MPEG  
IOControlMain  
hex  
IOControlMain is used for selecting/deselecting the appropriate data input  
interface and for setting up the serial data output interface. In serial input  
mode the coded audio data (Layer 2, Layer 3, AAC) is expected at the serial  
input interface SDIB (default). In the 8-bit-parallel input mode the PIO pins  
PI[19:12] are used.  
bit[15]  
MP3 block input selection  
0: MP3 block input mode OFF  
1: MP3 block input mode ON  
bit[14]  
Invert serial output clock (SOC)  
0 (reset)  
1
do not invert SOC  
invert SOC  
bit[13:12]  
bit[11]  
Reserved, must be set to zero  
Serial data output delay  
0 (reset)  
1
no additional delay (reset)  
additional delay of data related to word strobe  
bit[10]  
Reserved, must be set to zero  
bit[9:8]  
Input Select Main  
00 (reset) serial input at interface B  
01  
10  
11  
parallel input at PIO pins PI[19...12]  
reserved for future use  
reserved for future use  
bit[7:6]  
bit[5]  
Reserved, must be set to zero  
SDO Word Strobe Invert  
0
do not invert  
1 (reset)  
invert outgoing word strobe signal  
bit[4]  
Bits per Sample at SDO  
0 (reset)  
1
32 bits/sample  
16 bits/sample  
bit[3]  
bit[2]  
Reserved, must be set to zero  
Serial data input interface B clock invert (pin SIBC)  
0
not inverted (data latched at rising clock edge)  
incoming clock signal is inverted (data latched at  
falling clock edge)  
1 (reset)  
bit[1]  
bit[0]  
0 (reset)  
1
DEMAND MODE (PLL off, MAS 35x9F is clock  
master)  
BROADCAST MODE (PLL on, clock of MAS 35x9F  
locks on data stream)  
Validate  
0 (reset)  
1
no forced evaluation of control memory cells  
changes in control memory will become effective  
Bit[0] is reset after the DSP has recognized the changes. The controller  
should set this bit after the other D0 control memory cells have been initialized  
with the desired values.  
Micronas  
June 30, 2004; 6251-505-1DS  
33  
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