MAS 35x9F
DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:347
Interface Status Control (reset = 05
)
MPEG
InterfaceControl
hex
This control cell allows to enable/disable the data I/O interfaces. In addition,
the clock of the output data interface interfaces, S/PDIF and SDO, can be set
to a low-impedance mode.
bit[6]
S/PDIF input selection (used for download modules)
0 (reset)
1
select S/PDIF input 1
select S/PDIF input 2
bit[5]
Enable/disable S/PDIF output
0 (reset)
1
enable S/PDIF output
S/PDIF output (invalid)
bit[4]
bit[3]
Reserved, must be set to zero
Enable/disable serial data output SDO
0 (reset)
1
SDO valid data
SDO invalid data
bit[2]
Output clock characteristic (SDO and S/PDIF outputs)
0
low impedance
high impedance
1 (reset)
bit[1]
bit[0]
reserved, must be set to zero
1)
Enable/Disable SDI
0
enable
disable
1 (reset)
2
Both digital outputs, S/PDIF and I S, and the D/A converters may use the
decoded audio independent of each other.
Changes at this memory address must be validated by setting bit[0] of
D0:346
.
hex
D0:348
Oscillator Frequency (reset = 18432
)
All
OfreqControl
dec
bit[19:0]
oscillator frequency in kHz
In order to achieve a correct internal operating frequency of the DSP, the nom-
inal crystal frequency has to be deposited into this memory cell.
Changes at this memory address must be validated by setting bit[0] of
D0:346
.
hex
1)
Note: The pins SIC, SII, SID are switched to output mode, if bit [0] = 1 (Reset value).
34
June 30, 2004; 6251-505-1DS
Micronas
MICRONAS [ MICRONAS ]
