DATA SHEET
MAS 35x9F
2.11.4.Control of the Signal Processing
2.11.5.Start-up of the Audio Codec
Before starting the DSP, the controller should check
Before enabling the audio codec, the controller should
for a sufficient voltage supply (respective flag PUPn at
check for a sufficient voltage supply (respective flag
2
2
I C subaddress 76 ). The DSP is enabled by setting
PUPn at I C subaddress 76 ).
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2
the appropriate bit in the Control register (I C subad-
dress 6A ). The nominal frequency of the crystal
The audio codec is enabled by setting the appropriate
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2
oscillator must be written into D0:348. After an initial-
ization phase of 5 ms, the DSP data registers can be
bit at the Control register (I C subaddress 6A ). After
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an initialization phase of 5 ms, the DSP data registers
2
2
accessed via I C.
can be accessed via I C. The A/D and the D/A con-
verters must be switched on explicitly (register
2
Input and output control is performed via memory loca-
tion D0:346 and D0:347. The serial input interface
SDIB is the default. The decoded audio can be routed
to either the S/PDIF, the SDO and the analog outputs.
The output clock signal at pin CLKO is defined in
D0:349.
00 00
at I C subaddress 6C ). The D/A convert-
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ers may either accept data from the A/D converters or
the output of the DSP, or a mix of both (register
1)
2
00 06
and 00 07
at I C subaddress 6C ).
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Finally, an appropriate output volume (register
2
00 10
at I C subaddress 6C ) must be selected.
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All changes in the D0 memory cells become effective
synchronously upon setting the LSB of Main I/O Con-
trol (see Table 3–8 on page 32). Therefore, this cell
should always be written last.
2.11.6.Power-Down
All analog outputs should be muted and the A/D and
the D/A converters must be switched off (register
2
The digital volume control (see Table 3–8 on page 32)
is applied to the output signal of the DSP. The
decoded audio data will be available at the SPDO out-
put interface in the next version.
00 10
and 00 00
at I C subaddress 6C ). The
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DSP and the audio codec must be disabled (clear
DSP_EN and CODEC_EN bits in the Control register,
I C subaddress 6A ). By clearing both DC/DC
enable flags in the Control register (I C subaddress
2
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2
The DSP does not have to be started if its functions
are not required, e.g., for routing audio through the
codec part of the IC via the A/D and the D/A convert-
ers.
6A ), the microcontroller can power down the com-
plete system.
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1) mixer available in version A2 and later; in version
A1, please use selector 00 0F
.
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Micronas
June 30, 2004; 6251-505-1DS
21
MICRONAS [ MICRONAS ]
